Problem: simulation RTL --> vcd file (using NCSIM)

[Alvin80]

ncsim probe -create -shm

Hi everybody,
I'm working with NCSIM for simulating a hierarchical design at RT-level.
I'm especially interested in the activity of some register banks in the design.
Thus, I prepared the following script in order to annotate this activity into a vcd file.

cat > ncsim.tcl <<EOFF
database -open "namedb" -vcd -default -into "/space/CIC.vcd"
probe DUT -database "namedb" -all -depth all -waveform
EOFF

But at the end of the simulation, the activity of the desired registers (actually the output nets of the registers) is not in the VCD! Maybe there is some option that I can't find
At gate level I dont have any problems, but I need to simulate at that level.
I've already tried with the option -expand in the ncelab command...
My RTL code is written in verilog and the description of the register banks is as follows:
reg [27:0] x_reg_bank[9:0]; // X Registers bank
reg [27:0] y_reg_bank[9:0]; // Y Registers bank
reg [27:0] z_reg_bank[9:0]; // Z Registers bank

Do you know any solution for my problem?
Thanks in advance...

 

[RBB]

ncverilog vcd dump

I always dump a simvisoin database & not vcd

   initial
     begin
	    $shm_open;
	    $shm_probe("MAC");
     end

>> simvision waves.shm/ &

 

[Alvin80]

ncsim vcd

Thanks for the answer...
But I need to create a SAIF file and I cannot modify the RTL code (no DPFLI function or other pragma can be introduced). I know how I can translate vcd to SAIF....but I don't know how to create a SAIF from a shm database.
How can you create a SAIF file after a simulation with NCSIM (using shm database)?

 

[RBB]

simvisdbutil

You can't even change the testbench??

Added after 7 minutes:

If you can change the testbench there are PLIs for writing out a saif file directly.

If you cannot change the testbench then look into the dumpsaif command in the nc-sim manual, for dumping the saif file from a tcl script.

 

[aji_vlsi]

file format saif vcd

Hi,

Hi everybody,
I'm working with NCSIM for simulating a hierarchical design at RT-level.

reg [27:0] x_reg_bank[9:0]; // X Registers bank
reg [27:0] y_reg_bank[9:0]; // Y Registers bank
reg [27:0] z_reg_bank[9:0]; // Z Registers bank

Do you know any solution for my problem?
Thanks in advance...

As these are memories/MDAs, perhaps VCD doesn't capture them. Look in cdsdoc to see if there is any extra option to probe command. If not, maybe you can try converting SHM to VCS via shm2vcd command?

HTH
Ajeetha, CVC
Next SV course starting in Feb 09 end. See:
https://sv-verif.blogspot.com for details

 

[Alvin80]

dump vcd file simulation

Useful suggest!!
But I still have a problem.
I can dump a vcd file, but I find a vector format of the registers bank in my design.
Example:
$var wire 28 x! x_reg_bank[9] $end
$var wire 28 y! x_reg_bank[8] $end
$var wire 28 z! x_reg_bank[7] $end
$var wire 28 {! x_reg_bank[6] $end
$var wire 28 |! x_reg_bank[5] $end
$var wire 28 }! x_reg_bank[4] $end
$var wire 28 ~! x_reg_bank[3] $end
$var wire 28 !" x_reg_bank[2] $end
$var wire 28 "" x_reg_bank[1] $end
$var wire 28 #" x_reg_bank[0] $end

and in detailed...
b1000000000000000 #"

Then the vcd2saif command doesn't work correctly and I can't annotated the activity in the design (Design Compiler environment)
How can I avoid this format?
I would like to have a vcd format like that:
$var wire 1 #w x_reg_bank[0][27] $end
....
....
$var wire 1 #y x_reg_bank[0][0] $end

b1 #w
....
b0 #y

Any other idea? Is there any option in SimVision to capture the activity of each FF individually?
Thanks a lot...

 

[Alvin80]

vhdl code shm output

Solution found!!!

The problem was the NCSIM version.
I was using NCSIM 5.70 ... now I'm using NCSIM 8.1 and I don't have any troubles if I use this simulation flow :
- After ncvlog, ncelab...

ncsim +access+rwc -MESSAGES -CDSLIB cds.lib -LOG ../log/ncsim.log -BATCH -LICQUEUE -INPUT ncsim.tcl -RUN tbench.tb_top:behavioural

where ncsim.tcl is
database -open "wave.shm" -shm -into "../wave/wave.shm"
probe -create -shm -database wave.shm UT -all -memories -depth all

- Then I translate SHM database to VCD format...
simvisdbutil ../wave/wave.shm -addindices -output /space/CIC.vcd -vcd -overwrite
where -addindices is very important because "Adds indices for VHDL vectors and memories for VCD formatted output"

- Finally I translate VCD to SAIF format (using Synopsys command)...
vcd2saif -format verilog -i /space/CIC.vcd -instance "tb_top(behavioural)/DUT" -o ./SAIF/RTL/cic_01.saif

I hope that this post can be useful to other designers too.
Bye