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As expected, matched impedance on all interfaces for maximum bandwidth with rated capacitance in order to achieve guaranteed specs.

The includes Rt, CL & RL

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the 5.5V logic family typically have a 50 ohm nominal output impedance, thus with a 50 pF rated load the rated rise time is Tau=RC= 2.5ns

If non-50 ohm traces or twisted pairs are used then ringing is possible from reflections, if the path round trip delay the rise time,  so a std value 51 ohm  + 33 pF were suggested to provide matching in the upper band to null reflections in that spectrum of the step pulse.

An analog spectrum  for a pulse is often measured or computed as follows:  f-3dB=0.35/Tr (10~90%)     

Yet 1st order LPF is taken from the exponential step response 0 to 63% of target level which resolves to BW= 208 MHz and  not 10 to 90% value yet a comparator set to 50% will be faster and compute a high toggle rate.

So the equation for maximum toggle frequency or minimum pulse width, depends on the thresholds, which are typically 0 to 50%.

 We know that matched impedances eliminate reflections but also attenuate output 50% so a 250 ohm load to Vext/2 is the compromised Thevenin equiv. for this logic level driver for both SNR and BW. The two 500 ohm R's would mean only for that criteria, the load is 250 Ohms.  SNR meaning signal/noise ratio for the unknown noise.  SNR and BW are directly related to Shannon's Law and the Shannon Hartley Theorem for probability of errors.

 Yet your phantom pulse project used 1.2uH+40 Ohms with negative feedback on R so it becomes a high impedance current source mismatched to everything.  That's why it must be placed near the coil to avoid round trip prop delay> rise time.  The open loop BW with feedback must meet or exceed the modulator's closed loop BW spec and meet the SNR required for resolution and signal quality.  You must work backwards to determine SNR from the project requirements with additional margin for unknowns.  This is why design specs are far more important than picking parts by trial and error.

Now you know that 5V logic families are all 50 ohm Ohm (Vol/Io = Z nominal) +/-33% typ.) and this risetime indicates a toggle frequency of 200 MHz is maybe possible.  Now 3.6V max logic families are about 22 to 25 Ohms with the same wide tolerance and thus can go faster but typically operate at 3.3V and used in CMOS everywhere. There may be some exceptions but a standard family is the  74ALC and some uC rated for 3.6V max.  The 74ABT is in the older 5.5V family and the T just means it is TTL input or 2 Si diode levels of Vf for the nom. input threshold.  There are dozens of logic families as smaller lithography made devices faster. But they standardized Impedance or RdsOn at nominal rate voltage max for families like 5.5V, 3.6V and now lower levels with even lower Vol/Io = RdsOn such as in 1V CPU logic to achieve GHz speeds with lower gate capacitance too.  If you know RdsOn characteristics for any FET then this will make sense to avoid shootthru high currents in CMOS, thus the Vt thresholds will determine the dynamic RdsOn and Coss during transition and ideally you want this constant but in CMOS this is imperfect due to tolerances. The device characteristics with lower RdsOn FETs also have higher Coss or Cout unless made smaller by lithography or SiC or GaN.  This is also why some standards like impedance are never specified in datasheets , but implied if you compute Vol/Io, then you will understand why it must be standardized for speed and shoot-thru supply drawn current-noise reasons which create noise on Vdd unless suppressed by design.