Reply to thread

Message

Hello Tony,you succseeded to do a huge delay in the line below. i tried to create a 3section network also, but i get only 12nS shift.
what is the mathematical logic behind such a large delay?

[ATTACH=full]189912[/ATTACH]

[ATTACH=full]189913[/ATTACH]
[ATTACH=full]189911[/ATTACH]

[QUOTE="yefj, post: 1771735, member: 624287"] Hello Tony,you succseeded to do a huge delay in the line below. i tried to create a 3section network also, but i get only 12nS shift. what is the mathematical logic behind such a large delay? [ATTACH type="full"]189912[/ATTACH] [ATTACH type="full"]189913[/ATTACH] [ATTACH type="full"]189911[/ATTACH] [/QUOTE]

Verification

Part and Inventory Search

Analog Design
Analog Circuit Design
problem simulation delay line

Welcome to EDAboard.com

Reply to thread

Part and Inventory Search

Connect with us

Online statistics

Forum statistics