[SOLVED] problem simulating a simple counter in VHDL with Vivado

joseMiguel said:

hi guys,

here below the counter

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Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity count16 is 
port(
    CLK, nRESET, LOAD : in std_logic;
    D : in std_logic_vector(3 downto 0);
    Q : out std_logic_vector(3 downto 0));
end count16;
 
architecture archcount16 of count16 is
signal TEMP: unsigned(3 downto 0);
 
begin
    core : process(nRESET, CLK) begin
        if (nRESET = '0') then
            TEMP <=(others => '0');
        elsif (rising_edge(CLK)) then
            if LOAD = '1' then TEMP <= unsigned (D);
                            else TEMP <= TEMP + 1;
            end if;
            --TEMP <= TEMP +1;
        end if;
 
    end process core;
Q <= std_logic_vector (TEMP);
 
end archcount16;

---

the testbench

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Code VHDL - [expand]
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----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 15.05.2018 16:59:07
-- Design Name: 
-- Module Name: count16_tb - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity count16_tb is
    
--  Port ( );
end count16_tb;
 
architecture Behavioral of count16_tb is
 
COMPONENT count16
PORT(
    CLK : IN std_logic;
    nRESET : IN std_logic;
    LOAD: IN std_logic;
    D : IN std_logic_vector(3 downto 0);
    Q : OUT std_logic_vector(3 downto 0));
END COMPONENT;
 
    signal CLK : std_logic := '0';
    signal nRESET:  std_logic := '1';
    signal LOAD:  std_logic := '0';
    signal D : std_logic_vector(3 downto 0) := "0000";
    
    signal Q : std_logic_vector(3 downto 0);
    
    
    
    constant CLK_PERIOD : time := 20 ns;
begin
 
dut: count16 PORT MAP(
    CLK => CLK,
    nRESET => nRESET,
    LOAD => LOAD,
    D => D,
    Q => Q
);
 
RESET_generation: process
    begin
    nRESET <='0';
    wait for 170 ns;
    nRESET <= '1';
    wait;
end process RESET_generation;
 
CLK_generation: process
begin
    CLK <='0';
    wait for CLK_PERIOD/2;
    CLK <= '1';
    wait for CLK_PERIOD/2;
end process CLK_generation;
 
 
end Behavioral;

---

i succeed to launch the simulation but all is undefined.
there is no trace of the testbench

thank you so much for having read that post.

regards

joseMiguel

Click to expand...