#define CONFIG_REGISTER 0x40
#define CYCLE_COUNT_REGISTER 0x4A
#define STATUS_REGISTER 0x5E
#define MASK_REGISTER 0x74
void initCS5460A(){
unsigned char temp;
CLEARBIT(PORTD, PD_RESET); //Give CS5460 a h/w reset (PD4 = 0)
SETBIT(PORTB, PB_CLCS); // waste some time (2.9 us?)
SETBIT(PORTB, PB_CLCS); // waste some time (2.9 us?)
SETBIT(PORTD, PD_RESET); //
//The resistor on MS_RESET will add another delay. Need to wait some us after reset pulse before starting CS5461 comms
SETBIT(PORTB, PB_CLCS); // waste some time (2.9 us?)
SETBIT(PORTB, PB_CLCS); // waste some time (2.9 us?)
SETBIT(PORTB, PB_CLCS); // waste some time (2.9 us?)
tm_cs5460 = 0;
er_cs5460 = 0;
/*This function is used whenever CS5460A is reset so each time we need to reset the following values*/
SETBIT(ms_flags, MS_1ST_READ); //Used to discard first read
CLEARBIT(ms_flags, MS_CS_RESET); //Disable reset flag (it has been already done)
CLEARBIT(tb_flags, TB_INT_LOW);
//Output initialisation sequence to CS5461 via SPI
init_CS5460A_send_sequence();
}
void init_CS5460A_send_sequence(){
CLEARBIT(PORTB, PB_CLCS); //Enables SPI communication
//Resync
cs5460_send(0xFF);
cs5460_send(0xFF);
cs5460_send(0xFF);
cs5460_send(0xFE);
//soft reset
cs5460_Write_data(CONFIG_REGISTER, 0x000080);
//Resync
cs5460_send(0xFF);
cs5460_send(0xFF);
cs5460_send(0xFF);
cs5460_send(0xFE);
//configure (x10 gain for current)
cs5460_Write_data(CONFIG_REGISTER, 0x000061);
//set integration period (72 clocks)
cs5460_Write_data(CYCLE_COUNT_REGISTER, 0x000048);
//reset all bits in status register (IC* bit ignored)
cs5460_Write_data(STATUS_REGISTER, 0xFFFFF);
//set DRDY in mask register (for INT*)
cs5460_Write_data(MASK_REGISTER, 0x800000);
//start continuous computation cycles
cs5460_send(0xE8);
SETBIT(PORTB, PB_CLCS); //Disables SPI communication
}