Problem of post-simulation using ncverilog

[C. Lee]

failed attempt to annotate to non existent path

I finished gate-level synthesis. Then I dumped out .sdf and .v for gate-level simulation.

After I did the gate-level simulation with SDF timing annotation

I got the following error messages:

ncelab: *W,SDFNEP: Failed Attempt to annotate to non-existent path (IOPATH (posedge A) Y) of instance stimulus.pp.U89 of module XOR2X1 <./pingpong_syn.sdf, line 741>.

.....

line 741 of pingpong_syn.sdf is
(IOPATH (posedge A) Y (0.074:0.074:0.074) (0.080:0.080:0.080))


corresponding info in .v file is
XOR2X1 U89 ( .A(n10), .B(flip), .Y(n9) );

I have no idea how to fix them since I don't know the reason for these messages.
Do I forget to set up something ?

Thanks a lot.

--
ps,
module XOR2X1 is as follow:

module XOR2X1 (Y, A, B);
output Y;
input A, B;

xor I0(Y, A, B);

specify
// delay parameters
specparam
tplh$A$Y = 1.0,
tphl$A$Y = 1.0,
tplh$B$Y = 1.0,
tphl$B$Y = 1.0;

// path delays
if (B == 1'b1)
(A *> Y) = (tplh$A$Y, tphl$A$Y);
if (B == 1'b0)
(A *> Y) = (tplh$A$Y, tphl$A$Y);
if (A == 1'b1)
(B *> Y) = (tplh$B$Y, tphl$B$Y);
if (A == 1'b0)
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify

endmodule // XOR2X1

 

[firewire2035]

ncsim specify delay the clock problem

since your sdf is generated using liberty (.lib) file, there are some timing checks your verilog model does not support. the message you are seeing is for clock gating checks (STA).

you can choose to ignore the warnings.

 

[rsrinivas]

post synthesis gate level simulation using ncsim

while writing the sdf use the noedge option....
everything will go fine...
Regards
srinivas