Problem of bottom up flow in running DFTC

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hgby2209

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test_use_test_models

I use test_model in Hierarchical Scan Synthesis Flow .....
sub1 creat test_model1 (sub1.ctldb) & write out sub1.db
sub2 creat test_model2 (sub2.ctldb) & write out sub2.db

when I read .db & .ctldb in top level, the following Warning display:

Warning: Design 'sub1.db:sub1' comes before design 'sub1.ctldb:sub1' in the link_library; 'sub1.ctldb:sub1' will be ignored. (UIO-92)

Can anyone tell me how to fix this problem, when I need read in .db & .ctldb in top level ?
 

I find the solution for this issue :

set test_use_test_models true;# enable to creat & read test model, the test model will write out via "write -f db"

so if I set test_use_test_models to true, the I don't need to write test model.
The .db will include the test model.
 
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