problem modleing a delay locked loop in simulink

Thread starter vijay_nag
Start date Apr 26, 2005

Status: Not open for further replies.

Apr 26, 2005

vijay_nag

Advanced Member level 4

hi people!

i am a new member.
i am trying to model a delay locked loop in simulink. could anybody suggest me any solution? links regarding to the topic are also welcome.

thx,
vijay

Status: Not open for further replies.

Similar threads

P
Problem delay in switching current steering differential DAC
- Started by PhdSA
- Aug 15, 2024
- Replies: 5
Analog Circuit Design
Y
problem simulation delay line
- Started by yefj
- Mar 25, 2024
- Replies: 46
Analog Circuit Design
R
Cell delay decreases with decrease in supply voltage
- Started by riti
- Sep 27, 2024
- Replies: 1
Analog Circuit Design
Y
testing pulse delay in saturation and active states of a NPN
- Started by yefj
- Jun 14, 2024
- Replies: 34
Analog Circuit Design
T
Relation between closed loop and open loop gain of an opamp
- Started by The_pearl
- Jul 25, 2024
- Replies: 3
Analog Circuit Design

problem modleing a delay locked loop in simulink

vijay_nag

Advanced Member level 4

Similar threads

Privacy & Transparency

Privacy & Transparency