problem in Verilog with inout

[dexter_ex_2ks]

inout verilog testbench

Hello, a have a problem in Verilog.

I must do a testbench of a Asynchronous read write RAM.

The file is located at https://www.asic-world.com/examples....html#Single_Port_RAM_Asynchronous_Read/Write ,it's a tutorial.

Well my problem is : bit_vector data is inout,and my question is in the testbench how do I declare data (if i declare reg [DATA_WIDTH-1:0] data,I can't read/write data in the simulation,I know it is bi-directional,but I don't know how to declare it the testbench).I set we = 1, cs = 1 for writing ,and we = 0, oe = 1, cs = 1 , and I had changed the address and data (and the clock is ticking) but the data will not change.

So if I don't bother you,could you help me with the testbench,(I have no ideea how to work with bi-directional ports).



Thank you very much,and have a nice day.

 

[rberek]

verilog inout testbench

If you want a tristate bus in a testbench, declare the signal that you are connecting to the RAM's inout port as a tristate, driven by another register. Assume DATA_WIDTH is 16.

Therefore:

reg [15:0]   data_drvr;
tri [15:0]   data = data_drvr;

Now, assuming you've connected data to the RAM's inout port, you have a signal that can be driven by either the RAM or data_drvr.

When you want to drive data into the RAM, you put the data on data_drvr (i.e. data_drvr = 16'hcaca) and, at the same time, your testbench must set up the RAM model so its data bus is tristated (i.e. write mode).

To have the RAM drive data, you must use the testbench to put the RAM in read mode, and, at the same time, assign data_drvr = 16'hzzzz, so that data_drvr is tristated.

r.b.