arishsu
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- Sep 10, 2013
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Hi
there occured a problem with inout datatype declaration. The error says
"ERROR:HDLCompilers:247 - "IO_port.v" line 37 Reference to vector wire 'data_io' is not a legal reg or variable lvalue"
The code is as below
module IO_port(IOAR,in,out,IOW,IOR,device_addr,data_io,clk,data_acc
);
input in,out,IOR,IOW,clk;
input [7:0]IOAR;
inout wire[15:0]data_io;
inout wire[15:0]data_acc;
//wire [15:0]data_io,data_acc;
wire in_out;
output reg[7:0] device_addr;
assign in_out=(in || out);
assign device_addr=(in_out)?IOAR:8'bz;
always@(posedge clk)
begin
if(IOR)
data_acc=data_io;
else if(IOW)
data_io=data_acc;
else if(IOR&&IOW)
$display("operation error. IOR and IOW both active");
end
endmodule
there occured a problem with inout datatype declaration. The error says
"ERROR:HDLCompilers:247 - "IO_port.v" line 37 Reference to vector wire 'data_io' is not a legal reg or variable lvalue"
The code is as below
Code:
);
input in,out,IOR,IOW,clk;
input [7:0]IOAR;
inout wire[15:0]data_io;
inout wire[15:0]data_acc;
//wire [15:0]data_io,data_acc;
wire in_out;
output reg[7:0] device_addr;
assign in_out=(in || out);
assign device_addr=(in_out)?IOAR:8'bz;
always@(posedge clk)
begin
if(IOR)
data_acc=data_io;
else if(IOW)
data_io=data_acc;
else if(IOR&&IOW)
$display("operation error. IOR and IOW both active");
end
endmodule
Code: