vishi
Newbie level 3
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I want to use the for loop inside generate statement to be infinite as shown below. But the problem is I cannot stop or quit the loop at some condition using "disable text". neither i am able to use keyword "break".
It is showing an error:
My verilog code is:
It is showing an error:
please help me by solving this or suggest an alternative. thanksunexpected token: 'disable'
unexpected token: ';'
My verilog code is:
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 module top(a1,a3,wj,d4,d10,d2,dc,dtot); input [11:0]a1,a3,wj; input [3:0]d4; input [9:0]d10; input [1:0]d2; input [25:0]dc; output reg[25:0]dtot; reg [11:0]alpha1,alpha3; reg [25:0]dt,error; genvar i; generate for (i=1;i>0;i=i+1-1)begin:test assign a1[11:0]=alpha1[11:0]; assign a3[11:0]=alpha3[11:0]; calb_top t1(a1,a3,wj,d4,d10,d2,dc,dt,error,alpha1,alpha3); if(error==26'b00000000000000000000000000)begin disable test; //break; end end endgenerate assign dtot=dt; endmodule
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