VINAY_RAO
Junior Member level 2
Hi,
Recently i installed IC610 (cadence),but while running "icfb" i am getting many errors.When i give the comand "icfb" ,CIW opens but in between it ask for :"(delicense-7) couldnt get a license for schematics L.would you like to try to get a higherr tiered license to run this product?....(yes)..(no)..(always)..(never).."
By clicking yes,we wil get error..
The following appears in CIW and get aborted.
COPYRIGHT © 1992-2006 CADENCE DESIGN SYSTEMS INC. ALL RIGHTS RESERVED.
© 1992-2006 UNIX SYSTEMS Laboratories INC.,
Reproduced with permission.
This Cadence Design Systems program and online documentation are
proprietary/confidential information and may be disclosed/used only
as authorized in a license agreement controlling such use and disclosure.
RESTRICTED RIGHTS NOTICE (SHORT FORM)
Use/reproduction/disclosure is subject to restriction
set forth at FAR 1252.227-19 or its equivalent.
Program: @(#)$CDS: virtuoso.exe version 6.1.0 10/10/2006 14:09 (cds126047) $
Sub version: sub-version IC6.1.0.243 (32-bit addresses)
Loading geView.cxt
Loading LVS.cxt
Loading layerProc.cxt
Loading xlUI.cxt
Loading auCore.cxt
Loading schView.cxt
Loading selectSv.cxt
Loading vhdl.cxt
Loading seismic.cxt
Loading ams.cxt
Loading default bindkeys
Loading NCSU CDK 1.5.1 customizations...
loading vars from /home/vinaymm/cad_work/cadence_design/ncsu-cdk-1.5.1/cdssetup/cdsenv for tool adle
loading vars from /home/vinaymm/cad_work/cadence_design/ncsu-cdk-1.5.1/cdssetup/cdsenv for tool asimenv
loading vars from /home/vinaymm/cad_work/cadence_design/ncsu-cdk-1.5.1/cdssetup/cdsenv for tool ddserv
loading vars from /home/vinaymm/cad_work/cadence_design/ncsu-cdk-1.5.1/cdssetup/cdsenv for tool layout
loading vars from /home/vinaymm/cad_work/cadence_design/ncsu-cdk-1.5.1/cdssetup/cdsenv for tool schematic
loading vars from /home/vinaymm/cad_work/cadence_design/ncsu-cdk-1.5.1/cdssetup/cdsenv for tool ui
*WARNING* Cannot find /cad/cadence/ic6/tools.lnx86/dfII/etc/tools/cdsSpice directory to load environment variables
*WARNING* envSetVal: could not find tool[.partition] 'layoutOptimize.state'
loading vars from /home/vinaymm/cad_work/cadence_design/ncsu-cdk-1.5.1/cdssetup/cdsenv for tool layoutOptimize
loading vars from ~/.cdsenv for tool layoutOptimize
*WARNING* envSetVal: could not find tool[.partition] 'layoutOptimize.state'
loading vars from ~/.cdsenv for tool asimenv
*WARNING* (icLic-3) Could not get license Virtuoso_Schematic_Editor_L
*WARNING* (icLic-3) Could not get license Virtuoso_Schematic_Editor_L
(("schematic" nil)
("symbol" "schDisplaySymbolTemplateForm")
("abel" nil)
)
("functional" "behavioral" "system" "abel" "entity.vhdl"
"behavior.vhdl" "dataflow.vhdl" "structure.vhdl" "mixed.vhdl"
)
(("freeform"
((0 0)
(0 0)
)
(("[@instanceName]" "instance label" 0.08125 "stick" "NLPLabel")
("[@cellName]" "logical label" 0.08125 "stick" "NLPLabel")
)
)
("small"
((0.0 0.0)
(1.0 1.0)
)
(("[@instanceName]" "instance label" 0.075 "stick" "NLPLabel")
("[@cellName]" "logical label" 0.075 "stick" "NLPLabel")
)
)
("medium"
((0.0 0.0)
(1.5 1.5)
)
(("[@instanceName]" "instance label" 0.08125 "stick" "NLPLabel")
("[@cellName]" "logical label" 0.08125 "stick" "NLPLabel")
)
)
("large"
((0.0 0.0)
(2.0 2.0)
)
(("[@instanceName]" "instance label" 0.125 "stick" "NLPLabel")
("[@cellName]" "logical label" 0.125 "stick" "NLPLabel")
)
)
("2 by 1"
((0.0 0.0)
(1.5 0.75)
)
(("[@instanceName]" "instance label" 0.08125 "stick" "NLPLabel")
("[@cellName]" "logical label" 0.08125 "stick" "NLPLabel")
)
)
("1 by 2"
((0.0 0.0)
(0.75 1.5)
)
(("[@instanceName]" "instance label" 0.08125 "stick" "NLPLabel")
("[@cellName]" "logical label" 0.08125 "stick" "NLPLabel")
)
)
("alu"
((0.625 0.0)
(1.375 0.0)
(2.0 0.75)
(1.375 0.75)
(1.0 0.375)
(0.625 0.75)
(0.0 0.75)
)
(("[@instanceName]" "instance label" 0.08125 "stick" "NLPLabel")
("[@cellName]" "logical label" 0.08125 "stick" "NLPLabel")
)
)
("mux4"
((0.0 0.0)
(0.0 1.5)
(0.5 1.25)
(0.5 0.25)
)
(("[@instanceName]" "instance label" 0.08125 "stick" "NLPLabel")
("[@cellName]" "logical label" 0.08125 "stick" "NLPLabel")
)
)
("mux8"
((0.0 0.0)
(0.0 3.0)
(0.75 2.5)
(0.75 0.5)
)
(("[@instanceName]" "instance label" 0.08125 "stick" "NLPLabel")
("[@cellName]" "logical label" 0.08125 "stick" "NLPLabel")
)
)
)
("block"
("left" "input")
("right" "output")
("bottom" "inputOutput")
("top" "inputOutput")
)
(("Normal"
("floatingNets" "warning")
("floatingInput" "warning")
("floatingOutput" "ignored")
("floatingIO" "warning")
("floatingSwitch" "warning")
("shortedOutputs" "warning")
("unconnectedWires" "ignored")
("solderOnCrossover" "warning")
("instOverlap" "ignored")
("instOverlapValue" 0)
("maxLabelOffset" "ignored")
("maxLabelOffsetUU" 0.0)
("nameCollision" "warning")
("verilogSyntax" "ignored")
("VHDLSyntax" "ignored")
("instNameSyntax" "ignored")
("termNameSyntax" "ignored")
("netNameSyntax" "ignored")
)
("Logical Only"
("floatingNets" "warning")
("floatingInput" "warning")
("floatingOutput" "ignored")
("floatingIO" "warning")
("floatingSwitch" "warning")
("shortedOutputs" "warning")
("unconnectedWires" "ignored")
("solderOnCrossover" "ignored")
("instOverlap" "ignored")
("maxLabelOffset" "ignored")
("nameCollision" "ignored")
("verilogSyntax" "ignored")
("VHDLSyntax" "ignored")
("instNameSyntax" "ignored")
("termNameSyntax" "ignored")
("netNameSyntax" "ignored")
)
("Physical Only"
("floatingNets" "ignored")
("floatingInput" "ignored")
("floatingOutput" "ignored")
("floatingIO" "ignored")
("floatingSwitch" "ignored")
("shortedOutputs" "ignored")
("unconnectedWires" "warning")
("solderOnCrossover" "warning")
("instOverlap" "ignored")
("instOverlapValue" 0)
("maxLabelOffset" "ignored")
("maxLabelOffsetUU" 0.0)
("nameCollision" "ignored")
("verilogSyntax" "ignored")
("VHDLSyntax" "ignored")
("verilogSyntax" "ignored")
("instNameSyntax" "ignored")
("termNameSyntax" "ignored")
("netNameSyntax" "ignored")
)
("VHDL"
("nameCollision" "warning")
("verilogSyntax" "ignored")
("VHDLSyntax" "warning")
)
("Verilog"
("nameCollision" "warning")
("verilogSyntax" "warning")
("VHDLSyntax" "ignored")
)
)
(("schematic"
(("instName" "name"
(("objType" "inst")
("purpose" "cell")
)
)
("netName" "name"
(("objType" "net"))
)
("pinName" "name"
(("objType" "term"))
)
("master" "master")
("libName" "libName")
("cellName" "cellName")
("fontStyle" "font")
("fontHeight" "height")
("orient" "orient")
("partName" "partName")
("phyPartName" "phyPartName")
("power" "power")
("refDes" "refDes")
("technology" "technology")
("simMonitor" "schSimSignalName"
(("objType" "inst"))
)
)
)
("schematicSymbol"
(("pinName" "name"
(("objType" "net"))
)
("fontStyle" "font")
("fontHeight" "height")
("orient" "orient")
("layer" "layerName")
)
)
)
(("<state>"
("basic" "simState" "symbol")
)
("<time>:<state>"
("basic" "simState" "symbol")
)
("<name>=<state>"
("basic" "simState" "symbol")
)
("<name>=<time>:<state>"
("basic" "simState" "symbol")
)
)
("ta" "silos" "hspice" "shilo" "package"
".moduleInfo" "pcb" "verilog" "lai_verilog" "lmsi_verilog"
)
t
t
t
""
"lpr"
nil
nil
("reg" "time" "integer" "real" "expression")
nil
"query"
(("actHi"
("input" nil)
("output" nil)
("inputOutput" nil)
("switch" nil)
)
("actLo"
("input"
("basic" "tsgActLo" "symbol")
)
("output"
("basic" "tsgActLo" "symbol")
)
("inputOutput"
("basic" "tsgActLo" "symbol")
)
("switch"
("basic" "tsgActLo" "symbol")
)
)
("ieeeActLo"
("input"
("basic" "tsgIeeeActLoInp" "symbol")
)
("output"
("basic" "tsgIeeeActLoOut" "symbol")
)
("inputOutput"
("basic" "tsgIeeeActLoOut" "symbol")
)
("switch"
("basic" "tsgIeeeActLoOut" "symbol")
)
)
("clock"
("input"
("basic" "tsgClock" "symbol")
)
("output"
("basic" "tsgClock" "symbol")
)
("inputOutput"
("basic" "tsgClock" "symbol")
)
)
("actLoClock"
("input"
("basic" "tsgActLoClock" "symbol")
)
("output"
("basic" "tsgActLoClock" "symbol")
)
("inputOutput"
("basic" "tsgActLoClock" "symbol")
)
)
)
(("square"
("input"
("basic" "sympin" "symbolNN")
)
("output"
("basic" "sympin" "symbolNN")
)
("inputOutput"
("basic" "sympin" "symbolNN")
)
("switch"
("basic" "sympin" "symbolNN")
)
)
("circle"
("input"
("basic" "circle" "symbol")
)
("output"
("basic" "circle" "symbol")
)
("inputOutput"
("basic" "circle" "symbol")
)
("switch"
("basic" "circle" "symbol")
)
)
("block"
("input"
("basic" "blockipin" "symbol")
)
("output"
("basic" "blockopin" "symbol")
)
("inputOutput"
("basic" "blockiopin" "symbol")
)
("switch"
("basic" "blockiopin" "symbol")
)
)
)
"/cad/cadence/ic6/tools.lnx86/dfII/samples/symbolGen/default.tsg"
*WARNING* (icLic-3) Could not get license Virtuoso_Schematic_Editor_XL
Loading awv.cxt
*WARNING* There were no system .cdsplotinit files found.
*WARNING* There were no system .cdsplotinit files found.
Loading NCSU SKILL routines...
Loading oasis.cxt
ERROR (ADE-5066): Tool 'spectreS' has not been registered.
ERROR (ADE-5067): Unable to initialize tool 'spectreS'; either tool class is not
defined or tool is not registered.
*Error* The default SKILL generic function has not been defined for the function "asiEnvGetVar". Ensure that this function is called with the correct argument(s) (tool partition name).
How can i solve this problem...pl reply soon..
Thank you,
Regards,
VINAY RAO.
Recently i installed IC610 (cadence),but while running "icfb" i am getting many errors.When i give the comand "icfb" ,CIW opens but in between it ask for :"(delicense-7) couldnt get a license for schematics L.would you like to try to get a higherr tiered license to run this product?....(yes)..(no)..(always)..(never).."
By clicking yes,we wil get error..
The following appears in CIW and get aborted.
COPYRIGHT © 1992-2006 CADENCE DESIGN SYSTEMS INC. ALL RIGHTS RESERVED.
© 1992-2006 UNIX SYSTEMS Laboratories INC.,
Reproduced with permission.
This Cadence Design Systems program and online documentation are
proprietary/confidential information and may be disclosed/used only
as authorized in a license agreement controlling such use and disclosure.
RESTRICTED RIGHTS NOTICE (SHORT FORM)
Use/reproduction/disclosure is subject to restriction
set forth at FAR 1252.227-19 or its equivalent.
Program: @(#)$CDS: virtuoso.exe version 6.1.0 10/10/2006 14:09 (cds126047) $
Sub version: sub-version IC6.1.0.243 (32-bit addresses)
Loading geView.cxt
Loading LVS.cxt
Loading layerProc.cxt
Loading xlUI.cxt
Loading auCore.cxt
Loading schView.cxt
Loading selectSv.cxt
Loading vhdl.cxt
Loading seismic.cxt
Loading ams.cxt
Loading default bindkeys
Loading NCSU CDK 1.5.1 customizations...
loading vars from /home/vinaymm/cad_work/cadence_design/ncsu-cdk-1.5.1/cdssetup/cdsenv for tool adle
loading vars from /home/vinaymm/cad_work/cadence_design/ncsu-cdk-1.5.1/cdssetup/cdsenv for tool asimenv
loading vars from /home/vinaymm/cad_work/cadence_design/ncsu-cdk-1.5.1/cdssetup/cdsenv for tool ddserv
loading vars from /home/vinaymm/cad_work/cadence_design/ncsu-cdk-1.5.1/cdssetup/cdsenv for tool layout
loading vars from /home/vinaymm/cad_work/cadence_design/ncsu-cdk-1.5.1/cdssetup/cdsenv for tool schematic
loading vars from /home/vinaymm/cad_work/cadence_design/ncsu-cdk-1.5.1/cdssetup/cdsenv for tool ui
*WARNING* Cannot find /cad/cadence/ic6/tools.lnx86/dfII/etc/tools/cdsSpice directory to load environment variables
*WARNING* envSetVal: could not find tool[.partition] 'layoutOptimize.state'
loading vars from /home/vinaymm/cad_work/cadence_design/ncsu-cdk-1.5.1/cdssetup/cdsenv for tool layoutOptimize
loading vars from ~/.cdsenv for tool layoutOptimize
*WARNING* envSetVal: could not find tool[.partition] 'layoutOptimize.state'
loading vars from ~/.cdsenv for tool asimenv
*WARNING* (icLic-3) Could not get license Virtuoso_Schematic_Editor_L
*WARNING* (icLic-3) Could not get license Virtuoso_Schematic_Editor_L
(("schematic" nil)
("symbol" "schDisplaySymbolTemplateForm")
("abel" nil)
)
("functional" "behavioral" "system" "abel" "entity.vhdl"
"behavior.vhdl" "dataflow.vhdl" "structure.vhdl" "mixed.vhdl"
)
(("freeform"
((0 0)
(0 0)
)
(("[@instanceName]" "instance label" 0.08125 "stick" "NLPLabel")
("[@cellName]" "logical label" 0.08125 "stick" "NLPLabel")
)
)
("small"
((0.0 0.0)
(1.0 1.0)
)
(("[@instanceName]" "instance label" 0.075 "stick" "NLPLabel")
("[@cellName]" "logical label" 0.075 "stick" "NLPLabel")
)
)
("medium"
((0.0 0.0)
(1.5 1.5)
)
(("[@instanceName]" "instance label" 0.08125 "stick" "NLPLabel")
("[@cellName]" "logical label" 0.08125 "stick" "NLPLabel")
)
)
("large"
((0.0 0.0)
(2.0 2.0)
)
(("[@instanceName]" "instance label" 0.125 "stick" "NLPLabel")
("[@cellName]" "logical label" 0.125 "stick" "NLPLabel")
)
)
("2 by 1"
((0.0 0.0)
(1.5 0.75)
)
(("[@instanceName]" "instance label" 0.08125 "stick" "NLPLabel")
("[@cellName]" "logical label" 0.08125 "stick" "NLPLabel")
)
)
("1 by 2"
((0.0 0.0)
(0.75 1.5)
)
(("[@instanceName]" "instance label" 0.08125 "stick" "NLPLabel")
("[@cellName]" "logical label" 0.08125 "stick" "NLPLabel")
)
)
("alu"
((0.625 0.0)
(1.375 0.0)
(2.0 0.75)
(1.375 0.75)
(1.0 0.375)
(0.625 0.75)
(0.0 0.75)
)
(("[@instanceName]" "instance label" 0.08125 "stick" "NLPLabel")
("[@cellName]" "logical label" 0.08125 "stick" "NLPLabel")
)
)
("mux4"
((0.0 0.0)
(0.0 1.5)
(0.5 1.25)
(0.5 0.25)
)
(("[@instanceName]" "instance label" 0.08125 "stick" "NLPLabel")
("[@cellName]" "logical label" 0.08125 "stick" "NLPLabel")
)
)
("mux8"
((0.0 0.0)
(0.0 3.0)
(0.75 2.5)
(0.75 0.5)
)
(("[@instanceName]" "instance label" 0.08125 "stick" "NLPLabel")
("[@cellName]" "logical label" 0.08125 "stick" "NLPLabel")
)
)
)
("block"
("left" "input")
("right" "output")
("bottom" "inputOutput")
("top" "inputOutput")
)
(("Normal"
("floatingNets" "warning")
("floatingInput" "warning")
("floatingOutput" "ignored")
("floatingIO" "warning")
("floatingSwitch" "warning")
("shortedOutputs" "warning")
("unconnectedWires" "ignored")
("solderOnCrossover" "warning")
("instOverlap" "ignored")
("instOverlapValue" 0)
("maxLabelOffset" "ignored")
("maxLabelOffsetUU" 0.0)
("nameCollision" "warning")
("verilogSyntax" "ignored")
("VHDLSyntax" "ignored")
("instNameSyntax" "ignored")
("termNameSyntax" "ignored")
("netNameSyntax" "ignored")
)
("Logical Only"
("floatingNets" "warning")
("floatingInput" "warning")
("floatingOutput" "ignored")
("floatingIO" "warning")
("floatingSwitch" "warning")
("shortedOutputs" "warning")
("unconnectedWires" "ignored")
("solderOnCrossover" "ignored")
("instOverlap" "ignored")
("maxLabelOffset" "ignored")
("nameCollision" "ignored")
("verilogSyntax" "ignored")
("VHDLSyntax" "ignored")
("instNameSyntax" "ignored")
("termNameSyntax" "ignored")
("netNameSyntax" "ignored")
)
("Physical Only"
("floatingNets" "ignored")
("floatingInput" "ignored")
("floatingOutput" "ignored")
("floatingIO" "ignored")
("floatingSwitch" "ignored")
("shortedOutputs" "ignored")
("unconnectedWires" "warning")
("solderOnCrossover" "warning")
("instOverlap" "ignored")
("instOverlapValue" 0)
("maxLabelOffset" "ignored")
("maxLabelOffsetUU" 0.0)
("nameCollision" "ignored")
("verilogSyntax" "ignored")
("VHDLSyntax" "ignored")
("verilogSyntax" "ignored")
("instNameSyntax" "ignored")
("termNameSyntax" "ignored")
("netNameSyntax" "ignored")
)
("VHDL"
("nameCollision" "warning")
("verilogSyntax" "ignored")
("VHDLSyntax" "warning")
)
("Verilog"
("nameCollision" "warning")
("verilogSyntax" "warning")
("VHDLSyntax" "ignored")
)
)
(("schematic"
(("instName" "name"
(("objType" "inst")
("purpose" "cell")
)
)
("netName" "name"
(("objType" "net"))
)
("pinName" "name"
(("objType" "term"))
)
("master" "master")
("libName" "libName")
("cellName" "cellName")
("fontStyle" "font")
("fontHeight" "height")
("orient" "orient")
("partName" "partName")
("phyPartName" "phyPartName")
("power" "power")
("refDes" "refDes")
("technology" "technology")
("simMonitor" "schSimSignalName"
(("objType" "inst"))
)
)
)
("schematicSymbol"
(("pinName" "name"
(("objType" "net"))
)
("fontStyle" "font")
("fontHeight" "height")
("orient" "orient")
("layer" "layerName")
)
)
)
(("<state>"
("basic" "simState" "symbol")
)
("<time>:<state>"
("basic" "simState" "symbol")
)
("<name>=<state>"
("basic" "simState" "symbol")
)
("<name>=<time>:<state>"
("basic" "simState" "symbol")
)
)
("ta" "silos" "hspice" "shilo" "package"
".moduleInfo" "pcb" "verilog" "lai_verilog" "lmsi_verilog"
)
t
t
t
""
"lpr"
nil
nil
("reg" "time" "integer" "real" "expression")
nil
"query"
(("actHi"
("input" nil)
("output" nil)
("inputOutput" nil)
("switch" nil)
)
("actLo"
("input"
("basic" "tsgActLo" "symbol")
)
("output"
("basic" "tsgActLo" "symbol")
)
("inputOutput"
("basic" "tsgActLo" "symbol")
)
("switch"
("basic" "tsgActLo" "symbol")
)
)
("ieeeActLo"
("input"
("basic" "tsgIeeeActLoInp" "symbol")
)
("output"
("basic" "tsgIeeeActLoOut" "symbol")
)
("inputOutput"
("basic" "tsgIeeeActLoOut" "symbol")
)
("switch"
("basic" "tsgIeeeActLoOut" "symbol")
)
)
("clock"
("input"
("basic" "tsgClock" "symbol")
)
("output"
("basic" "tsgClock" "symbol")
)
("inputOutput"
("basic" "tsgClock" "symbol")
)
)
("actLoClock"
("input"
("basic" "tsgActLoClock" "symbol")
)
("output"
("basic" "tsgActLoClock" "symbol")
)
("inputOutput"
("basic" "tsgActLoClock" "symbol")
)
)
)
(("square"
("input"
("basic" "sympin" "symbolNN")
)
("output"
("basic" "sympin" "symbolNN")
)
("inputOutput"
("basic" "sympin" "symbolNN")
)
("switch"
("basic" "sympin" "symbolNN")
)
)
("circle"
("input"
("basic" "circle" "symbol")
)
("output"
("basic" "circle" "symbol")
)
("inputOutput"
("basic" "circle" "symbol")
)
("switch"
("basic" "circle" "symbol")
)
)
("block"
("input"
("basic" "blockipin" "symbol")
)
("output"
("basic" "blockopin" "symbol")
)
("inputOutput"
("basic" "blockiopin" "symbol")
)
("switch"
("basic" "blockiopin" "symbol")
)
)
)
"/cad/cadence/ic6/tools.lnx86/dfII/samples/symbolGen/default.tsg"
*WARNING* (icLic-3) Could not get license Virtuoso_Schematic_Editor_XL
Loading awv.cxt
*WARNING* There were no system .cdsplotinit files found.
*WARNING* There were no system .cdsplotinit files found.
Loading NCSU SKILL routines...
Loading oasis.cxt
ERROR (ADE-5066): Tool 'spectreS' has not been registered.
ERROR (ADE-5067): Unable to initialize tool 'spectreS'; either tool class is not
defined or tool is not registered.
*Error* The default SKILL generic function has not been defined for the function "asiEnvGetVar". Ensure that this function is called with the correct argument(s) (tool partition name).
How can i solve this problem...pl reply soon..
Thank you,
Regards,
VINAY RAO.