Problem in generating the schematic view of a module

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pcjoshi02

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there is problem in generating the schematic view of a module.this module is simulated in modelsim and its rtl view is also generated using ise but i cant generate its schematic view................
 

Re: Problem in synthesis

Try running a synthesis or syntax check in your synthesis/PAR program...

ie. ISE for xilinx, Quartus for Altera FPGAs. Sometimes Modelsim and other simulation tools will be more tolerant to certain syntax compared to the actual synthesis tool. If you have a synthesis problem, the schematic module will not generate.
 

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