I have a serious problem in driving ad676.
I use correct timing in sample and clk pins.
But sometimes after
sample=1;
delay_us(3);
sample=0;
while(busy==0);
while(busy==1) ///This while spend more than 16 cycles
{
clk=1;
delay_us(2);
clk=0;
delay_us(2);
}
clk=1;
delay_us(2);
clk=0;
delay_us(2);
I dont know if you have worked with this ADC but , when you asset SAMPLE pin hign busy will be 0 and it never happens that when you assert SAMPLE high ,Afterward BUSY will go up,
Your while loop is a infinite loop and never exit from this loop.
Sorry not a good reply