Problem in creating logic to electrical connect module in verilogams in Cadence ADE

Hi,



I am trying to make a logic to electrical connect module that can convert logic ( '1' or '0') at the input side to electrical pulses at the output side, implementing in verilog-ams, its required for one of the project that I am doing. But, the problem that I am having is that, its running and simulation is taking place, but irrespective of whether I give '1 or a logic '0'', the output is staying at 818.18mV. My Vhigh= 1.8 V and Vlow= 0v.

I am attaching the code that I am trying to implement....

(Taken from the designers guide only....... link: **broken link removed**)


// Logic to Electrical Connect Module
//
// Version 1a, 1 June 04
//
// Olaf Zinke
//
// Downloaded from The Designer's Guide Community (www.designers-guide.org).
// Post any questions on www.designers-guide.org/Forum.
// Taken from "The Designer's Guide to Verilog-AMS" by Kundert & Zinke.
// Chapter 4, Listing 18.

`include "disciplines.vams"
`timescale 1ns / 10ps

connectmodule d2a (out, in);
parameter real v0 = 0.0; // output voltage for a logic 0 (V)
parameter real v1 = 5.0; // output voltage for a logic 1 (V)
parameter real vx = 2.5; // output voltage for a logic x (V)
parameter real vz = 5.0; // output voltage for a logic z (V)
parameter real r0 = 1k from (0:inf); // output resistance for a logic 0 (Ohms)
parameter real r1 = 1k from (0:inf); // output resistance for a logic 1 (Ohms)
parameter real rx = 100 from (0:inf); // output resistance for a logic x (Ohms)
parameter real rz = 1M from (0:inf); // output resistance for a logic z (Ohms)
parameter real tr=1n from [0:inf); // rise time (s)
parameter real tf=1n from [0:inf); // fall time (s)
input in;
output out;
logic in;
electrical out;
real v, r;

assign in = in;

initial begin
case(in)
1'b0: begin v = v0; r = r0; end
1'b1: begin v = v1; r = r1; end
1'bx: begin v = vx; r = rx; end
1'bz: begin v = vz; r = rz; end
endcase
end

always @in begin
case(in)
1'b0: begin v = v0; r = r0; end
1'b1: begin v = v1; r = r1; end
1'bx: begin v = vx; r = rx; end
1'bz: begin v = vz; r = rz; end
endcase
end

analog
V(out) <+ transition(v, 0, tr, tf) + transition(r, 0, tr, tf)*I(out);
endmodule


I am trying to implement it in cadence ADE with AMS simulator.

Regards,

Indrajit

Indrajit Das said:

Hi,

I am trying to make a logic to electrical connect module that can convert logic ( '1' or '0') at the input side to electrical pulses at the output side, ...

I am trying to implement it in cadence ADE with AMS simulator.

Regards,

Indrajit

Click to expand...

You might want try asking in the LinkedIn Verilog-AMS group -

https://www.linkedin.com/groups?gid=2119051

I actually invented the connect module methodology, but Cadence didn't implement it properly, so I can't say what will or won't work in practice. If you are a licensed Cadence user you should be able to find examples in their on-line help.