problem in an addition in a vhdl code

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Hello,

I have written the following code but I do not take the right results from the addition: met <=met+monada;
I think that the problem is that I have the signal met twice.
Specifically, I take that the output nn is equal to 1..
At first I had that my signals and the output are this type: "sfixed" beacause I wanted to add fixed point numbers but then the following error was appeared:
expression has 7 elements, but must have 6 elements
Then I increased the number of elements and it appeared this error: expression has 8 elements, but must have 7 elements

Code VHDL - [expand]
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee.numeric_std.all;
USE ieee.std_logic_signed.all;
 
ENTITY adder IS
    PORT (z:IN SIGNED(2 DOWNTO 0) :="001";
          nn:OUT  signed (5 DOWNTO 0));
END adder;
 
ARCHITECTURE behavior OF adder IS
signal met:signed(5 DOWNTO 0);
signal monada:signed(2 DOWNTO 0);
signal meta:signed(5 DOWNTO 0);
 
BEGIN
    PROCESS(met)
--        variable count: integer range 26 downto 0;
 
 
BEGIN
 
--monada <=  to_sfixed (1,monada);
FOR i IN 1 TO 25 LOOP
     
   met <=met+1;
--   met <=meta;
END LOOP;   
 
 
FOR i IN 1 TO 5 LOOP
 IF(z=i) THEN
   nn<=met;
 END IF;
END LOOP;
 
END process;
 
END behavior;


What is my error?What I have to do?Please help me!!Thank you very much in advance..
 
Last edited by a moderator:

I dont know which line you're talking about has an error, because you dont point it out.

But I suspect the initial problem comes from your for loop. A signal is only assigned when a process suspends. So in your code, met <= met + 1; occurs 25 times, but as the signal wont be updated, it is just a single + 1, not 25x +1.

So can you please rephrase your question, with the problem marked in your code.
 

Thank you TrickyDicky for your reply..Sorry that I did not mention it but yes the error is in the line met <= met + 1..
I read carefully your answer and thank you for your information about what is happening in my signal..What change do you think I have to do?
Should I change the type of "met" instead of determining it as a signal?And what kind of change?
 

I have posted all my code. It is in my first post.
This code is a try that I do so as to make the operation of the addition and I tried to do it because I try to write a code and there the variable 'met' is a fixed point number and I added it with a fixed point number.
 

From this code - I guess you have a software background?
There is a major problem with the code in that the process is sensitive to a signal that is updated inside itself - so this process will just run in an infinite loop in simulation and you'll probably hit the iteration limit.
Initialisation is that - the value given to a signal/variable when the simulation is started. In your code, it has no initialisation value, so as the signed type is an array of std_logic it will initialise to "UUUUUU" (uninitialised) as per the type definition (uninitialised values take the leftmost value).

If you want to increase this value by 25, why not simply write:

met <= met + 25?

I suggest you go back to a VHDL tutorial, preferably one that talks about digital logic too. If your digital logic knowledge is lacking - I suggest you read up on that to. When you're more confident, draw your circuit out on paper. HDL stands for hardware description language, so if you dont know what the circuit should be, how do you expect to describe it?
 

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