Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Problem: digital error correction in pipelineADC

Status
Not open for further replies.
P

philipwang

Advanced Member level 4
Full Member level 1
Joined
Mar 30, 2005
Messages
102
Helped
13
Reputation
26
Reaction score
2
Trophy points
1,298
Location
Sz China
Activity points
2,161
Who can supply a full digital error correction arithmetic in 1.5b/stage pipelineADC?
Detailed derivation is the best. Thanks!
 

I have many IEEE papers and other papers about pipelineADC error correction and calibration. I will upload them in the IEEE Papers, Study Papers board.You can find some papers that can help you.
 

you can find in "cmos data converters for communication"
 

This is a paper about pipelined ADC error. Perhaps can help you .
 

thanks
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top