Problem delay in switching current steering differential DAC

[PhdSA]

Hi,

I have designed a 3 bit binary current steering DAC with diferential PMOS and NMOS current source. This DAC uses a diifferential gate as a switch wich are connected to buffer transistor, for pmos current the buffer is PMOS transistor and for NMOS current source the buffer is NMOS transisor, as can be seen in figure below. Each of this buffer transistor connected to differential NMOS transistor of differential amplifier.After doing the layout, a delay appears during switching when connecting the PMOS buffer transistor to the NMOS transistor of the differential amplifier, as displayed in figure below. Thus, this delay could be due to a few factors that relate to differences in drive strength, parasitics, and timing mismatches between the PMOS and NMOS paths. Can you help me by giving me some strategies to address this issue, if i insert a block between the buffer and NMOS transistor or using body biasing. I try to connect the bulk of NMOS transistor to the VDD, however this solution can't help me. I'm so gratefull if you can help me.

 

[dick_freebird]

Begin with that your "differential" logic may in fact
be "complementary", the difference being in both
amplitude and skew. Your glitches are still high and
this says you may have more drive than you need.

If your logic is not CML / SCL true differential then
stop pretending and deal.

Your level-skew looks like it corresponds to about
20ps of time-skew in the "LH" and "HL". That to me
is round-off error (maybe not to you) and demands
high quality representation of all actors (like layout
loading, which you have noted but not fully defeated).

The other inflections are still unexplained and might
or might not have common roots.

 

[PhdSA]

Hello,
Thank you very much for your suggestion. However, when i connected this block with current mirror that provide both PMOS and NOS current, the output signal'curve is destructed and changed , as you can seen below:
the glitch problem appears more, more disymmetry in switching what can i do in this case, i'm so gratefull if you can helpe me

--- Updated Aug 27, 2024 ---

Have you any reference of CML circuit that i should insert between the binary and the switch, i'm so gratefull if you can send me some paper or book. Thank you

 

[BradtheRad]

Those glitches remind me of unpredictable spikes that show up in asynchronous counters (and which made it necessary to develop synchronous counters). My simulation illustrates the glitchy ramp waves although I suppose you generate your waveforms differently and at higher speed. Can you filter out the glitches? Via capacitive or inductive?

 

[dick_freebird]

That's an interestiong point, have you looked at
counter edge synchrony (likely not ideal, improbable
to dead-match HL and LH across PVT even if at nom).
If gross (like ripple counter) re-registering could line
them up better (subject to HL, LH match there).

 

[sidun.av]

@PhdSA, as I understand from your previous tread, this problem appears only after layout?
Did you go through all critical nodes to inspect for coupling capacitance to agressors (such as clock) and excessive parasitics in general?
Apart from that, I can suggest checking the waveforms of your transmission gates for any delays/overlaps.
Hopefully, that helps.