problem compiling testbench "Unknown formal identifier "Width". "

Forgive me, I'm sure there is a simple solution to this but I am still very much a beginner with VHDL and am learning as I go along for a Digital Design course I'm currently taking. I'm running into a weird compiling error and was hoping I could get some help sorting through this. I have pasted the testbench and code I am testing underneath. I would greatly appreciate any form of assistance.

I'm trying to compile a testbench on ModelSim and I'm getting the following error:
Unknown formal identifier "WIDTH". The ModelSim compiler cites the line I typed out in red as providing the error.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity gcd_tb is
end gcd_tb;

architecture TB of gcd_tb is

constant WIDTH : positive := 16;
constant TIMEOUT : time := 1 ms;

signal clkEn : std_logic := '1';
signal clk : std_logic := '0';
signal rst : std_logic := '1';
signal go : std_logic := '0';
signal done : std_logic;
signal x : std_logic_vector(WIDTH-1 downto 0) := (others => '0');
signal y : std_logic_vector(WIDTH-1 downto 0) := (others => '0');
signal output : std_logic_vector(WIDTH-1 downto 0);

begin

UUT : entity work.gcd(FSM_D1)
generic map (
WIDTH => WIDTH)
port map (
clk => clk,
rst => rst,
go => go,
done => done,
x => x,
y => y,
output => output);

clk <= not clk and clkEn after 20 ns;

process

function GCD (x, y : integer)
return std_logic_vector is

variable tmpX, tmpY : integer;
begin

tmpX := x;
tmpY := y;
while (tmpX /= tmpY) loop
if tmpX < tmpY then
tmpY := tmpY-tmpX;
else
tmpX := tmpX-tmpY;
end if;
end loop;

return std_logic_vector(to_unsigned(tmpX, WIDTH));

end GCD;

begin

clkEn <= '1';
rst <= '1';
go <= '0';
x <= std_logic_vector(to_unsigned(0, WIDTH));
y <= std_logic_vector(to_unsigned(0, WIDTH));
wait for 200 ns;

rst <= '0';
for i in 0 to 5 loop
wait until clk'event and clk = '1';
end loop; -- i

for i in 1 to 2**WIDTH-1 loop

x <= std_logic_vector(to_unsigned(i, WIDTH));

for j in 1 to 2**WIDTH-1 loop

go <= '1';
y <= std_logic_vector(to_unsigned(j, WIDTH));
wait until done = '1' for TIMEOUT;
assert(done = '1') report "Done never asserted." severity warning;
assert(output = GCD(i, j)) report "Incorrect GCD" severity warning;
go <= '0';
wait until clk'event and clk = '1';

end loop;
end loop;

clkEn <= '0';
report "DONE!!!!!!" severity note;

wait;

end process;

end TB;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ctrl1_package.all;
use work.datapath1_package.all;

entity gcd is
generic (
WIDTH : positive := 16);
port (
clk : in std_logic;
rst : in std_logic;
go : in std_logic;
done : out std_logic;
x : in std_logic_vector(WIDTH-1 downto 0);
y : in std_logic_vector(WIDTH-1 downto 0);
output : out std_logic_vector(WIDTH-1 downto 0));
end gcd;


architecture FSM_D1 of gcd is

signal x_sel, x_en : std_logic;
signal y_sel, y_en : std_logic;
signal x_lt_y, x_ne_y : std_logic;
signal output_en : std_logic;
signal tmpX,tmpY : std_logic_vector(WIDTH-1 downto 0);
signal xBuff,yBuff : std_logic_vector(WIDTH-1 downto 0);
signal XsubY,YsubX : std_logic_vector(WIDTH-1 downto 0);

begin
Datapath: datapath1 port map(
x => x,
y => y,
clk => clk,
output => output);

Ctrl : ctrl1 port map(
clk => clk,
x_lt_y => x_lt_y,
x_ne_y => x_ne_y,
x_sel => x_sel,
x_en => x_en,
y_sel => y_sel,
y_en => y_en,
output_en => output_en);


end FSM_D1;

library ieee;
use ieee.std_logic_1164.all;
package gcd_package is
component gcd
generic (
WIDTH : positive := 16);
port (
clk : in std_logic;
rst : in std_logic;
go : in std_logic;
done : out std_logic;
x : in std_logic_vector(WIDTH-1 downto 0);
y : in std_logic_vector(WIDTH-1 downto 0);
output : out std_logic_vector(WIDTH-1 downto 0));
end component;
end gcd_package;


Thanks alot for any help!
Also, please let me know if there is other information I should provide as this is my first post on the forum.

Re: problem compiling testbench "Unknown formal identifier "Width". "

fpganovice said:

UUT : entity work.gcd(FSM_D1)
generic map (
WIDTH => WIDTH)

Click to expand...

See, you are trying to pass a generic parameter on top of your tb, which is not allowed. You are allowed to only pass value directly to your uut, this error should be cleared

Re: problem compiling testbench "Unknown formal identifier "Width". "

xtcx said:

See, you are trying to pass a generic parameter on top of your tb, which is not allowed. You are allowed to only pass value directly to your uut, this error should be cleared

Click to expand...

This answer doesnt make any sense. The code in question has no problems. You can pass generics into a UUT from a testbench without any problems, and there is no problems having generics on a testbench.

The code compiled just fine for me, when I re-ordered your entities. Have you compiled the code in the correct order?

Re: problem compiling testbench "Unknown formal identifier "Width". "

Oops, I missed seeing this declaration

constant WIDTH : positive := 16;

Click to expand...