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problem about s/h SFDR

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fencl

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Hi all.
i'm working on a s/h for 100M/S 14bit adc.since my SFDR is come with SNDR,that's means catch the output data and use matlab code for calculation.just like for whole adc dynamic data.no matter with Hspice or Spectre.
But,there's seems someone directly got SFDR for s/h in cadence,my question is after s/h ,the signal isn't a continuous signals ,what's your way for SFDR calculation?
BTW,if for setting time,is the max dc different voltage with vcm(for eg.vrefp,vrefn) input better or sine input with max frequence and mag better for setting accurate.since the latter can't measure exactly input value for certain output hold signal.my op is 110db and 1g GBW,is it ok ?
And for snr,if we want 12bit ENOB,that means about 72db ,what's snr value should s/h offer at least?
 

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