lhlbluesky
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differential dynamic comparator
in per stage 1.5bit pipelined ADC, dynamic comparator can be used to decrease power consumption; as we know , dynamic comparator has three types: resistive dynamic comparator, differential pair dynamic comparator and capacitive dynamic comparator. i want to know, what is the difference of the three kind of comparators?
and in paper "A MISMATCH INSENSITIVE CMOS DYNAMIC COMPARATOR FOR
PIPELINE A/D CONVERTERS", differential pair dynamic comparator is analyzed, and it says that its offset is smaller than resistive dynamic comparator, why?
and how to calculate and design the threshold voltage of the differential pair dynamic comparator ?can it be the same with the resistive dynamic comparator, just with (W/L)ref=(1/4)(W/L)in, or is there other method?pls help me.
thanks all for reply.
in per stage 1.5bit pipelined ADC, dynamic comparator can be used to decrease power consumption; as we know , dynamic comparator has three types: resistive dynamic comparator, differential pair dynamic comparator and capacitive dynamic comparator. i want to know, what is the difference of the three kind of comparators?
and in paper "A MISMATCH INSENSITIVE CMOS DYNAMIC COMPARATOR FOR
PIPELINE A/D CONVERTERS", differential pair dynamic comparator is analyzed, and it says that its offset is smaller than resistive dynamic comparator, why?
and how to calculate and design the threshold voltage of the differential pair dynamic comparator ?can it be the same with the resistive dynamic comparator, just with (W/L)ref=(1/4)(W/L)in, or is there other method?pls help me.
thanks all for reply.