PROBLEM: 74ls645 sim model?

hello to all,

I am trying to design a simulation model of an 74ls641 buffer. I have done and test it without success and I am a bit stuck. When I assert low not_g and set low dir I don't see the output bidira equal to the input bidirb. I would appreciate any help.

Here is my code:

entity TI74LS645 is

port(
BIDIRA: inout std_logic_vector(7 downto 0);
BIDIRB: inout std_logic_vector(7 downto 0);
NOT_G: in std_logic;
DIR: in std_logic
);

end entity TI74LS645;

architecture BEHAVIOURAL of TI74LS645 is

begin

BUF_PROC: process( NOT_G, DIR, BIDIRA, BIDIRB)
begin
if ( (NOT_G = '0') and (DIR = '0') )then
BIDIRA <= BIDIRB;
elsif ( (NOT_G = '0') and (DIR = '1') )then
BIDIRB <= BIDIRA;
else
BIDIRB <= "ZZZZZZZZ";
BIDIRA <= "ZZZZZZZZ";
end if;
end process BUF_PROC;

end architecture BEHAVIOURAL;

------------------------------------AND NOW TESTBENCH----

entity TI74LS64Xtb is

end entity TI74LS64Xtb;

architecture BEHAVIOURAL of TI74LS64Xtb is

signal sig_bidira_745: std_logic_vector(7 downto 0);
signal sig_bidirb_745: std_logic_vector(7 downto 0);
signal sig_not_g_745: std_logic;
signal sig_dir_745: std_logic;

begin

TI74LS645_top: entity work.TI74LS645(behavioral)
port map(
BIDIRA => sig_bidira_745,
BIDIRB => sig_bidirb_745,
NOT_G => sig_not_g_745,
DIR => sig_dir_745);


sig_not_g_745 <= '1', '0' after 200 ns,'0' after 400ns,'0' after 600ns, '1' after 800ns;
sig_dir_745 <= '0', '0' after 200ns, '1' after 400ns, 'X' after 600 ns, 'X' after 800ns;
sig_bidirb_745 <= "ZZZZZZZZ", "10101010" after 150ns, "XXXXXXXX" after 390ns;
sig_bidira_745 <= "ZZZZZZZZ", "10101010" after 410ns, "XXXXXXXX" after 590ns;

end architecture BEHAVIOURAL;