ProASIC3 clock distribution issues

jmcnabb · Mar 16, 2022

Hey friends. I'm working with a ProASIC3L, and I keep getting these errors:
Planning global net placement...

Error: PLC004: No legal global assignment could be found. Some global nets have shared

instances, requiring them to be assigned to overlapping global regions.

Global Nets Whose Drivers Are Limited to Quadrants or Which Have No Valid Locations:

|--------------------------------------------|

|Global Net |Valid Driver Locations |

|--------------------------------------------|

|GLA |(None)

|--------------------------------------------|

|GLB |(None)

|--------------------------------------------|

|RST_N_c |(None)

|--------------------------------------------|

Info: Consider relaxing the constraints for these nets by removing region constraints,

unassigning fixed cells and I/Os, relaxing I/O bank assignments, or using input

buffers without hardwired pad connections.

Error: PLC003: No legal global assignment could be found because of complex region and/or IO

technology constraints.

Error: PLC005: Automatic global net placement failed.

INFO: See the GlobalNet Report from the Reports option of the Tools menu for information about

the global assignment.

The Layout command failed ( 00:00:01 )

The GLA and GLB signals come from a PLL block and are then passed down a few module layers to all the different components in the design. I'm kinda a rookie to clock management and tbh dont really know how to approach debugging. Anyone got any advice for me?

ads-ee · Mar 16, 2022

Based on what little you posted from the reports, you have too many clocks in the design using to many global nets in a region.

Do you have location constraints that force logic from different clock domains into the same quadrant?

You might try increasing the number of globals allowed. I don't recall the setting that allows that. The ProASIC3L setting for globals defaults to 8 (IIRC) setting it to 12 can help (max is 16 but sometimes that will cause designs to fail P&R).

ProASIC3L has something like 3-4 quadrant globals, and 6 chip-wide globals. There is segmentation in the global networks, but from what I've seen the software doesn't seem to take advantage of this. You should carefully read the ProASIC3L FPGA Fabric User's Guide to get the full details.

BTW I consider it rude to cross post to other forums without informing users.