stanford
Full Member level 2
If we write verilog like this with async set/reset, does the synthesis tool use FF with this priority? (reset has higher priority than enable)
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If we were to write the code like this, will the tool use a different FF with enable being the higher priority?
Code:
always @(posedge clk or posedge reset or posedge enable)
begin
if (reset)
out <= 1'b0;
else if (enable)
out <= 1'b1;
else
out <=a & b;
end
================================================================================================
If we were to write the code like this, will the tool use a different FF with enable being the higher priority?
Code:
always @(posedge clk or posedge reset or posedge enable)
begin
if (enable)
out <= 1'b0;
else if (reset)
out <= 1'b1;
else
out <=a & b;
end