Nov 18, 2011 #1 S sun_ray Advanced Member level 3 Joined Oct 3, 2011 Messages 772 Helped 5 Reputation 10 Reaction score 5 Trophy points 1,298 Activity points 6,828 Can anyone draw a 4:1 priority mux that in synthesized using an if elesif statement? Please provide the RTKL of the 4:1 mux also, if possible.
Can anyone draw a 4:1 priority mux that in synthesized using an if elesif statement? Please provide the RTKL of the 4:1 mux also, if possible.
Nov 18, 2011 #2 V vivek_p Advanced Member level 4 Joined Feb 16, 2010 Messages 115 Helped 10 Reputation 24 Reaction score 9 Trophy points 1,298 Activity points 2,009 //Verilog Code for 4X1 Priority Mux module pr_mux4 (a,b,c,d,sel,out); input a,b,c,d; input [1:0] sel; output out; reg out; always@(a or b or c or d or sel) begin if (sel == 2'b00) out = a; else if(sel == 2'b01) out = b; else if (sel == 2'b10) out = c; else out = d; end endmodule; Please find the figure: Attachments pr_mux.bmp 541 KB · Views: 165
//Verilog Code for 4X1 Priority Mux module pr_mux4 (a,b,c,d,sel,out); input a,b,c,d; input [1:0] sel; output out; reg out; always@(a or b or c or d or sel) begin if (sel == 2'b00) out = a; else if(sel == 2'b01) out = b; else if (sel == 2'b10) out = c; else out = d; end endmodule; Please find the figure:
Nov 19, 2011 #3 S sun_ray Advanced Member level 3 Joined Oct 3, 2011 Messages 772 Helped 5 Reputation 10 Reaction score 5 Trophy points 1,298 Activity points 6,828 Well done vivek_p. Can you please let me know the reason it is said that the priority mux is used to provide priority on late arriving signal. For nexample in the above code the signal named a is a late arriving signal.
Well done vivek_p. Can you please let me know the reason it is said that the priority mux is used to provide priority on late arriving signal. For nexample in the above code the signal named a is a late arriving signal.