priority mux diagram necessary with the RTL also

[sun_ray]

Can anyone draw a 4:1 priority mux that in synthesized using an if elesif statement? Please provide the RTKL of the 4:1 mux also, if possible.

 

[vivek_p]

//Verilog Code for 4X1 Priority Mux

module pr_mux4 (a,b,c,d,sel,out);

input a,b,c,d;
input [1:0] sel;
output out;

reg out;

always@(a or b or c or d or sel)
begin
if (sel == 2'b00)
out = a;

else if(sel == 2'b01)
out = b;

else if (sel == 2'b10)
out = c;

else
out = d;
end

endmodule;

Please find the figure:

 

[sun_ray]

Well done vivek_p.

Can you please let me know the reason it is said that the priority mux is used to provide priority on late arriving signal. For nexample in the above code the signal named a is a late arriving signal.