what is the difference between priority encoder and encoder(without priority) vhdl program and when do we need to use k-map simplification for here?
this is the prog i know for priority encoder:
entity pri_encoder is
port( r: in std_logic_vector(3 downto 0);
code: out std_logic_vector(1 downto 0);
active: out std_logic);
end pri_encoder;
architecture arch of pri_encoder is
begin
code <= "11" when (r(3)=’1’) else
"10" when (r(2)=’1’) else
"01" when (r(1)=’1’) else
"00";
active <= r(3) or r(2) or r(1) or r(0);
end arch;
Is this way of writing in the architecture correct:
entity pri_encoder is
port( r: in std_logic_vector(3 downto 0);
code: out std_logic_vector(1 downto 0);
active: out std_logic);
end pri_encoder;
architecture arch of pri_encoder is
begin
code <= "11" when "1000" else
"10" when "0100" else
"01" when "0010" else
"0000";
active <= r(3) or r(2) or r(1) or r(0);
end arch;