Prevent RTL Optimization Genus

[toastrstroodel]

Hello,

I am trying to prevent pretty much all RTL optimization in the synthesis process with my design. I would like to keep the elaborated design exactly the way it is and map it to my std cell library. In genus, I am attempting to use the preserve attribute. TCL command: set_attribute preserve true <instance_name>. The problem is, I need to run this command after elaboration, but before synthesis. If I try to run it before syn_gen, the rtl optimization stage, I get errors that say you cannot preserve an unmapped or partially mapped instance. However, syn_map, the stage of mapping to the standard cell library, must be executed after syn_gen. So pretty much, the only time I am allowed to preserve an instance is after RTL optimization, which doesn't help at all. Is there another command that I am missing in the user guide to preserve the instance or design post-elaboration and pre-synthesis? Any help is appreciated.

Thanks!

 

[ThisIsNotSam]

that makes no sense. you are actively trying not to synthesize the design!

may you explain why? what is the goal? best idea I can think of is turning the syn effort to low and see what happens, but even low effort is quite smart.

 

[toastrstroodel]

Yes, I understand it's very strange. The library uses a very uncommon form of logic where pretty much a node could be considered unnecessary by a synthesis tool (i.e is always at logic 0) but still carries important information (in this case, a fixed common mode voltage needed for the next gate)

Is it not possible to keep an elaborated design with the generic gates exactly the way it is and simply map that to a std cell library?

 

[ThisIsNotSam]

that wouldn't be synthesis, that would be translation. I think no tool can do that automatically, they are too smart for that. depending on how complex your design is, perhaps you could achieve that by hand. I am sure the results are going to be not great.