Preserve design (signal, instance, etc) in synopsys DC

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rybackguo

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I have a design that contains redundant structures and I do not want synopsys DC to optimize my design logic away, but the tool remove the circuits by default.

How can I ask DC not to remove my logic? Also how to reduce the optimization effort? (I have very relaxed requirements for other constraints.)



Thank you!
 

It depends on what kind of optimization it is applying to these design elements.
Not sure at what stage you wish to apply this and if your startpoint is RTL or netlist.

If netlist youc an use "set_dont_touch" constraints to preserve these elements. IF RTL depending on the opto you will need to disable the settings that lead to this redundancy removal - for eg, constants, unloaded flops etc
 

Hi rybackguo,
As englishdogg mentioned you can apply the dont_touch attribute at various levels. You can do it at the RTL/netlist level or at the SDC constraints level and also at the DC script level.

Embedded in the RTL/Netlist, have a synopsys dc_script_begin attribute
// synopsys dc_script_begin,
// dont_touch -cell {te0 te1 te2 te3}
// synopsys dc_script_end

The following is a way to do this by the script and apply dont_touch to the various hierarchical blocks
dc_shell> current_design top
dc_shell> set_dont_touch {BLOCK2/ALU3 BLOCK2/CPU4}
dc_shell> compile

You can also do a report_design to see which parts of the design are under preserve state . .

Cheers!
Mike
 

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