david753
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I was invloved in implementing BPSK decoder.
The structure of circuit is like as following description.
BPSK Signal --> AD9057 (8 bits) --> FPGA
The FPGA can retrieve the base band date only if digital out has 1 bit variant.
So, there is 1/256=-44dbm sensitivity, ideally.
But, unfortunately, the system only work at -18dbm.
There is -44-(-18)=-26 db loss.
Why there is 26 db signal loss?
I consider to replace the internal reference with external reference by ADR431 or ADR03.
Is it useful to increase the sensitivity?
Does anyone have any experience related this issue?
The structure of circuit is like as following description.
BPSK Signal --> AD9057 (8 bits) --> FPGA
The FPGA can retrieve the base band date only if digital out has 1 bit variant.
So, there is 1/256=-44dbm sensitivity, ideally.
But, unfortunately, the system only work at -18dbm.
There is -44-(-18)=-26 db loss.
Why there is 26 db signal loss?
I consider to replace the internal reference with external reference by ADR431 or ADR03.
Is it useful to increase the sensitivity?
Does anyone have any experience related this issue?