Precise sine wave with variable shift

Status
Not open for further replies.

kitepassion

Member level 3
Joined
Jan 5, 2010
Messages
54
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Location
US
Visit site
Activity points
1,659
Hi to all,

I need to generate in the FPGA a very precise sine wave. The frequency of the sinewave is constant while the Amplitude and the Phase change.

The aim is not to utilize the sinewave to drive a DAC but instead to use it for signal processing inside the FPGA.

Now... an example: I have a 2.5 KHz sine, the phase can be between 0 and pi. The phase resolution and the frequency resolution are very important. For one period of sine I need 100 points per period.

What can be the best method to generate such a sine?

Tank you
K
 

What you want to create is an implementation of a Numerically Controlled Oscillator: https://en.wikipedia.org/wiki/Numerically_controlled_oscillator
These are routinely built into FPGAs and only a modest number of bits for the phase accumulator (~24-48 bits are typical) is required to achieve some pretty remarkable performance!
 

I already tried with a DDS but I had not so much success: poor frequency resolution, and poor SNR of the output sine. It is the first time I heard of an NCO. Is it similar to a DDS?
 

Aye - it is... (sorry, you're getting the hasty one-line answers while I run between tasks on the weekend
A DDS is essentially the "NCO architecture" - nicely integrated with whatever Analog Devices (etc) have decided a nice compromise between speed/cost/resolution is, with (often) an integrated DAC too. They're wonderful gadgets, but yes, they often suffer from the foibles you pointed out.

There's nothing wrong with the principle though - and if you don't need to venture into the analog domain (i.e. you're doing everything numerically with your FPGA) you can achieve stellar performance by making the various precisions arbitrarily high - the sine table length and precision and the phase accumulator can be independantly set to whatever you like/need - generally while trading off speed/FPGA resources required. At 2.5 KHz you shouldn't have a problem.
 

Status
Not open for further replies.
Cookies are required to use this site. You must accept them to continue using the site. Learn more…