pre and postsynthesis simulation mismatch please help

Hello everyone,
I have some problem in my gate level netlist simulation. My RTL code simulation is working fine but gate level simulation is not working(getting XXX state). But the design successfully passes the formal verification. Please give me some solution.

Follow the X's back to the root cause

A simple solution to avoid these 'X's are
1) Check all the control registers are not 'x' in reset state (this fixes most of the issues)
2) Make sure that you are not getting 'X' on any control bus (in normal simulation too like data valid etc...)

If still 'X' Comes then you need to back trace to the root cause

you need to follow the coding guide lines to avoid these

Hi,

You also can check the rams output. Normally you need to initial the ram's contents. You can ask your vendor how to do it.

Thanks for the reply.
Sir, i am a student doing my final year project, and i am implementing viterbi decoder in ASIC.
The data in RAM and other registers is in '0' state when reset.
The address to the RAM is been generated from the block called TBU which has the problem of x-state (therefore, the data from the RAM is not coming correctly). This TBU block has a shift register kind of logic in it. The always block in the module has the appropriate sensitivity list specified(as per my knowledge) in it to avoid the pre and post simulation mismatch.
And I haven't given any SDF file during simulation. Is this the reason why i am not getting o/p? I am simulating the gatelevel netlist obtained from DC in VCS(have added the libraries also). There is no error reported by the synthesis tool except few known warnings. Waiting for your reply.

Well if the RAM is causing the X's then it either needs to be initialized to some value and/or write to before read from.

This problem can come If all of your Registers or the signals in the always blocks are not initialised properly . If you have not initialised any of the Signals used in the always block you will get X and it will propagate throughout your Design . Try checking that . Also try checking IF Clock is coming properly .