PRBS Generator - VHDL Implementation

ishailesh · Aug 29, 2013

I am trying to implement a PRBS generator as show in diagram.

My top level module is

Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity prbs is
    Port ( clock : in  STD_LOGIC;
            reset : IN std_logic := '0';
           prbsout : out  STD_LOGIC);
end prbs;

architecture Behavioral of prbs is

COMPONENT dff
	PORT(
		clock : IN std_logic;
		reset : IN std_logic := '0';
		din : IN std_logic := '1';          
		dout : OUT std_logic
		);
	END COMPONENT;
signal temp : std_logic := '0';
begin

genreg : for i in 0 to 3 generate
begin
instdff : entity dff port map ( clock , reset , din(i) , dout(i));
end generate genreg;

main : process(clock)

begin
for j in 0 to 3 loop
if ( j /= 0) then
din(j) <= dout(j-1);
else
din(j) <= dout(0) xor dout(2);
temp <= dout(j);
end if;
end loop;
prbsout <= temp;
end process main;

end Behavioral;

and dff entity is

Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dff is
    Port ( clock : in  STD_LOGIC ;
           reset : in  STD_LOGIC := '0';
           din : in  STD_LOGIC := '1';
           dout : out  STD_LOGIC);
end dff;

architecture Behavioral of dff is

begin
process(clock)

begin
if clock'event and clock = '1' then
  if reset = '0'  then
  --  dout <= din;
	else
    dout <= '0';	
	 end if;
	end if;
end process;


end Behavioral;

I am using Xilinx ISE 10.1 on 64 bit Windows 7.

Now when i synthesize dff then synthesis tool returns no error.
But when i synthesize prbs then it show errors.

ERROR:HDLParsers:3313 - "E:/IIT/modulator/source/prbs.vhd" Line 51. Undefined symbol 'din'. Should it be: in or min?
ERROR:HDLParsers:1209 - "E:/IIT/modulator/source/prbs.vhd" Line 51. din: Undefined symbol (last report in this block)
ERROR:HDLParsers:3313 - "E:/IIT/modulator/source/prbs.vhd" Line 51. Undefined symbol 'dout'. Should it be: out?
ERROR:HDLParsers:1209 - "E:/IIT/modulator/source/prbs.vhd" Line 51. dout: Undefined symbol (last report in this block)
ERROR:HDLParsers:3324 - "E:/IIT/modulator/source/prbs.vhd" Line 51. IN mode Formal din of entity with no default value must be associated with an actual value.
ERROR:HDLParsers:3313 - "E:/IIT/modulator/source/prbs.vhd" Line 59. Undefined symbol 'din'. Should it be: in or min?
ERROR:HDLParsers:1209 - "E:/IIT/modulator/source/prbs.vhd" Line 59. din: Undefined symbol (last report in this block)
ERROR:HDLParsers:3313 - "E:/IIT/modulator/source/prbs.vhd" Line 59. Undefined symbol 'dout'. Should it be: out?
ERROR:HDLParsers:1209 - "E:/IIT/modulator/source/prbs.vhd" Line 59. dout: Undefined symbol (last report in this block)

FvM · Aug 29, 2013

I review the error message and see that they are very plausible. Every signal used in the design must be defined before.

Look e.g. at "reset". It would be usually an input port of the top entity. But the only port signals are clock and prbsout. So reset is both undefined and undriven.

ishailesh · Aug 29, 2013

FvM said:
I review the error message and see that they are very plausible. Every signal used in the design must be defined before.

Look e.g. at "reset". It would be usually an input port of the top entity. But the only port signals are clock and prbsout. So reset is both undefined and undriven.

I assigned these signals some default value. Still error remains same

TrickyDicky · Aug 29, 2013

No, Dout does not exist in prbs.vhd. you have not defined it, therefore you get errors. It exists as a port on the dff entity, but you have not decalred it locally.

FvM · Aug 29, 2013

I assigned these signals some default value. Still error remains same

Reset has a default value in entity dff. To make use of it, you must omit the reset port signal in the comonent instantiation.

This might work for reset, although it involves a risk that the RRBS generator is stuck in all zero state. But errors are also for missing din and dout signals, without them, the design can never work.

ishailesh · Aug 30, 2013

Thanks @FvM and @TrickyDicky for your useful advice.
It worked.

Here i am posting a snapshot of prbs

My modified code is

Code:

-- Engineer: Shailesh Singh
-- Module Name:    prbs 
-- Project Name:   modulator

-- Description: 
--To make it of N bit replace existing value of N with desired value of N
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity prbs is
    Port ( pclock : in  STD_LOGIC;
	        preset : IN std_logic := '0';
           prbsout : out  STD_LOGIC);
end prbs;

architecture Behavioral of prbs is

COMPONENT dff is
	PORT(
		dclock : IN std_logic;
		dreset : IN std_logic;
		din : IN std_logic ;          
		dout : OUT std_logic 
		);
	END COMPONENT;
	

signal dintern : std_logic_vector (4 downto 1); --Change value of N to change size of shift register
signal feedback : std_logic := '0';

begin

instdff : dff port map (pclock , preset , feedback , dintern(1));
genreg : for i in 2 to 4 generate --Change Value of N Here to generate that many instance of d flip flop
begin
instdff : dff port map ( pclock , preset , dintern(i-1) , dintern(i));
end generate genreg;

main : process(pclock)

begin
	if pclock'event and pclock = '1' then	
			if preset = '0'  then
				if dintern /= "0" then
					
					feedback <= dintern(1) xor dintern(3); -- For N equals four;
					--feedback <= dintern(4) xor dintern(5) xor dintern(6) xor dintern(8); -- For N equals eight;
					--feedback <= dintern(11) xor dintern(13) xor dintern(14) xor dintern(16); -- For N equals sixteen;
					--feedback <= dintern(1) xor dintern(2) xor dintern(22) xor dintern(32); -- For N equals thirty two						
			   
				else
				feedback <= '1';
				end if;
			end if;	 			 						
	end if;	
end process main;

prbsout <= dintern(4) ; --Change Value of N Here to take output to top entity 

end Behavioral;

and dff module is

Code:

----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Module Name:    dff - Behavioral 
-- Project Name:  modulator
-- Description: instantiate code in prbs module
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity dff is
    Port ( dclock : in  STD_LOGIC ;
           dreset : in  STD_LOGIC ;
           din : in  STD_LOGIC;
           dout : out  STD_LOGIC);
end dff;

architecture Behavioral of dff is

begin
process(dclock)

begin
	if dclock'event and dclock = '1' then
		if dreset = '0' then
			dout <= din;
      else
			dout <= '1';
		end if;
	end if;
end process;


end Behavioral;

But i am not getting output.
In top level entity i am getting always 1 at prbsout signal.

When i try to simulate then it becomes undefined.

What i am missing?

PRBS Generator - VHDL Implementation

ishailesh

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FvM

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ishailesh

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TrickyDicky

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ishailesh

FvM

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ishailesh

ishailesh

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