Hi angu.
In my opnion, u need to understand the ASIC design flow first.
Then, u'll know where and how to do it.
Basically, u have ur RTL code.
Next, perform RTL simulation (called Functional Simulation or pre-synthesis simulation)
Once you get the code and functionality is correct. U need to synthesize the RTL code. Whether it is using ASIC library or FPGA library upto the Designer.
After tht u'll get gate-netlist circuit or synthesized circuit.
Next, u take this gate-netlist circuit and perform another simulation called Timing Simulation (Post-synthesis simulation).
Now, u'll have a gate delay. Not so accurate. But good enough to check ur circuit performance. To get more accurate timing information, u need to do layout design and do parasitic extraction.
I hope u get what I'm trying to say here.
The best is u need to have an ASIC flow chart. U can get this from any ASIC books or just google it.
Hope it helps.