power wave form via prime time px

Jupiter_2900 · Aug 7, 2015

hi every one

i have a simple design named "hardenSBox" comprised of two parts 1)sequential part, so-called "regOut" which has 8 DFF 2)combinational part so-called "lookUp". i haved showed in following section, verilog code related to each part:

Code Verilog - [expand]
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module hardenSbox(indexX,indexY,sel,clk,reset,out_port);
input [3:0] indexX;
input [3:0] indexY;
input clk;
input reset;
output [7:0] out_port;
wire [7:0] temp;
input sel;
wire sel;
 
    lookUp ins_lookup(.indexX(indexX),.indexY(indexY),.sel(sel),.outPut(temp));
    regOut ins_regout(.inp(temp),.outp(out_port),.clk(clk),.reset(reset));
endmodule

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module regOut (inp,outp,clk,reset);
input [7:0] inp;
input clk;
input reset;
output [7:0] outp;
reg [7:0] outp;
 
always@(posedge clk)
  begin
    if(reset == 1)
        outp<=0;
    else
        outp<=inp;
 
  end
endmodule

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module lookUp ( indexX ,indexY ,sel ,outPut );
 
output [7:0] outPut ;
reg [7:0] outPut ;
 
input [3:0] indexX ;
wire [3:0] indexX ;
input [3:0] indexY ;
wire [3:0] indexY ;
input [0:0] sel ;
wire [0:0] sel ;
 
reg [3:0] x1_15;
reg [4:0] x2_32;
 
reg [4:0] x1_31;
reg [3:0] x2_16;
//}} End of automatically maintained section
reg [7:0] z2;
reg [7:0] z1;
// -- Enter your statements here -- //
always @(*)
    begin
        if (sel == 0)
            begin//<32,15>
               case ({indexX,indexY})
                8'h0:
                begin
                x1_15 = 4'd9;
                x2_32 = 5'd3  ; 
                end
                8'h01:
                begin
                x1_15 = 4'd4;
                x2_32 = 5'd28  ;
                end
                8'h02:
                begin
                x1_15 = 4'd14;
                x2_32 = 5'd23  ;
                end
                8'h03:
                begin
                x1_15 = 4'd3;
                x2_32 = 5'd27  ;
                end
                8'h04:
                begin
                x1_15 = 4'd2;
                x2_32 = 5'd18  ;
                end
                8'h05:
                begin
                x1_15 = 4'd2;
                x2_32 = 5'd11  ;
                end
                8'h06:
                begin
                x1_15 = 4'd6;
                x2_32 = 5'd15 ;
                end
                8'h07:
                begin
                x1_15 = 4'd2;
                x2_32 = 5'd5  ;
                end
 
.....
                8'hff:
                begin
                x1_31 = 5'd22;
                x2_16  = 4'd6  ;
                end
                default:
                begin
                x1_31 = 5'd00;     
                x2_16  = 4'd00  ;
                end
               endcase
               
               z1 = x1_31;
 
                           z2 = {4'b0,x2_16} + (~{4'b0,(x1_31)}) + 1 ;
          
               if (z2[7] == 1)
                  z2 = z2 + 16;
               if (z2[7] == 1)
                  z2 = z2 + 16;
 
 
               z2 = 31*z2;
               z2 = {4'b0,z2[3:0]};
 
               outPut = 31*z2 + z1;
                
            end
            
    end
    
endmodule

as shown in above section the lookup module is much larger than regOut module. based on final operations the in lookup module, i expect that, power consumption in lookup portion be larger than regout but its quite oposite and power consumption in regOut module is dominate factor in a way that lookup module's power consumption can ignore, hows that possible ???
i synthesize my code with Design compiler and i check post synteses simulation with Model sim and everything work correct. i obtained, power consumption wave form via Prime Time Px and in following section i have brought , used script.

Code Bash - [expand]
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set  power_enable_analysis TRUE
set power_analysis_mode time_based
cd /root/Desktop/hardenSBox
set search_path {. /root/Desktop/harden_V2 /root/Desktop/harden_V3}
 
set link_library [list * ./db/NangateOpenCellLibrary_45nm.db]
 
remove_design -all
read_verilog ./out/hardenSbox_dc_netlist.v
 
read_ddc -netlist ./out/hardenSbox.ddc 
read_sdc ./out/hardenSbox.sdc
read_parasitics ./out/hardenSbox.spef
read_vcd ./modelsim/switching.vcd -strip_path [B][COLOR="#FF0000"]Tb/sub1/ins_lookup[/COLOR][/B] [B][COLOR="#00FFFF"]Tb/sub1/ins_regout[/COLOR][/B]
current_design hardenSbox
link  
set_power_analysis_options -waveform_output ./prime_time/wavePostLayout -waveform_format fsdb -include top
update_power

i first run above script with red color portion and in second run, i substitute red part with blue one and separately i dipict output fsdb files via nWave tool, and i see suprisingly that ins_lookup power wave form is much smaller than the ins_regout ???? did i do something wrong ?? this result is not reasonable at all , plllzzz help how could i get correct waveform power ???

ads-ee · Aug 7, 2015

Jupiter_2900 said:
as shown in above section the lookup module is much larger than regOut module. based on final operations the in lookup module, i expect that, power consumption in lookup portion be larger than regout but its quite oposite and power consumption in regOut module is dominate factor in a way that lookup module's power consumption can ignore, hows that possible ???

Power consumption in CMOS is directly related to switching, every time a signal switches between high/low logic values it uses power. The FFs are switching based on the clock and there are a number of gates in those flops that are changing state each time the output has to change state. If you look at the switching of every gate in the combination section you'll probably find that there aren't that many gates switching each clock cycle.

Jupiter_2900 · Aug 7, 2015

hi ads-ee

my combinational logic comprise of some arithmatic likes multiplication, adder, sub , i think these functions have comparable activity factor with these 8 flip flop. besides my lookup logic is much larger than regout logic, and i think its glitch activity is much higher ??!!

power wave form via prime time px

Jupiter_2900

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