anonymous.
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How to create/synthesize a power up sequence for a specific design?
Let's take for example a DDR3 memory controller. Power up or Reset initialization sequence requires asserting/deasserting multiple signals, each for a specific amount of time or requires that some signals become asserted a specific amount of time before other signals, and so on.
How is this done in hardware? and how can it transfer control to normal logic after finishing the required sequence? and how to write a synthesizable VHDL code for something like this? I could use wait keyword bus this is not synthesizable. any help?
Let's take for example a DDR3 memory controller. Power up or Reset initialization sequence requires asserting/deasserting multiple signals, each for a specific amount of time or requires that some signals become asserted a specific amount of time before other signals, and so on.
How is this done in hardware? and how can it transfer control to normal logic after finishing the required sequence? and how to write a synthesizable VHDL code for something like this? I could use wait keyword bus this is not synthesizable. any help?