Power table

D.A.(Tony)Stewart said:

Energy per cycle depends on all internal and load values of C with conservation of energy meaning the loss in inverter.
The risetime depends on Ron*C.
estimate Power * Tau {rise or fall in 1/2 cycle}

If you do not know C you cannot compute this dyn. power.

Pavg = (Pdynamic + Pstatic) = Ctot * Vdd ^2 * f + I.leak*Vdd



RdsOn only affects risetime and not power dissipation, yet internal C rises with lower RdsOn and thus voltage must be reduced with lower RdsOn to reduce power. Another reason is lower Vdd means lower Vt and RdsOn affects shootthru current in transition so Vdd max:min range reduces with Vdd (max)

Historic Anecdotal experience
This is why high voltage (18V) CMOS 4000 series started in the '70's had Rout > 3kOhm ~18V.
Then along came 74HC family =5.5V max est. 50 ohm +/-50%
Then 74ALC family used in modern uC limited to 3.6V est. 22~25 Ohm +/-50% output impedance Zol=Vol/Io
Internal inverters have much smaller load C so higher RdsOn, and lower internal C thus lower energy and lower dynamic power per gate.

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