Power table

[Saati]

Hi all,
I want to simulate inverter standard cell in 180nm and verify rise_power and fall_power based on the rise time and output capacitanc.
I use virtuoso for simulation.

Based on PDK document the power is related to short circuit current. but i don't know how to find this. how to calculate integral of short circuit current?


The power table for inverter standard cell is below.

Thanks & regards
saati

 

[D.A.(Tony)Stewart]

Energy per cycle depends on all internal and load values of C with conservation of energy meaning the loss in inverter.
The risetime depends on Ron*C.
estimate Power * Tau {rise or fall in 1/2 cycle}

If you do not know C you cannot compute this dyn. power.

Pavg = (Pdynamic + Pstatic) = Ctot * Vdd ^2 * f + I.leak*Vdd



RdsOn only affects risetime and not power dissipation, yet internal C rises with lower RdsOn and thus voltage must be reduced with lower RdsOn to reduce power. Another reason is lower Vdd means lower Vt and RdsOn affects shootthru current in transition so Vdd max:min range reduces with Vdd (max)

Historic Anecdotal experience
This is why high voltage (18V) CMOS 4000 series started in the '70's had Rout > 3kOhm ~18V.
Then along came 74HC family =5.5V max est. 50 ohm +/-50%
Then 74ALC family used in modern uC limited to 3.6V est. 22~25 Ohm +/-50% output impedance Zol=Vol/Io
Internal inverters have much smaller load C so higher RdsOn, and lower internal C thus lower energy and lower dynamic power per gate.

 

[Saati]

Energy per cycle depends on all internal and load values of C with conservation of energy meaning the loss in inverter.
The risetime depends on Ron*C.
estimate Power * Tau {rise or fall in 1/2 cycle}

If you do not know C you cannot compute this dyn. power.

Pavg = (Pdynamic + Pstatic) = Ctot * Vdd ^2 * f + I.leak*Vdd



RdsOn only affects risetime and not power dissipation, yet internal C rises with lower RdsOn and thus voltage must be reduced with lower RdsOn to reduce power. Another reason is lower Vdd means lower Vt and RdsOn affects shootthru current in transition so Vdd max:min range reduces with Vdd (max)

Historic Anecdotal experience
This is why high voltage (18V) CMOS 4000 series started in the '70's had Rout > 3kOhm ~18V.
Then along came 74HC family =5.5V max est. 50 ohm +/-50%
Then 74ALC family used in modern uC limited to 3.6V est. 22~25 Ohm +/-50% output impedance Zol=Vol/Io
Internal inverters have much smaller load C so higher RdsOn, and lower internal C thus lower energy and lower dynamic power per gate.

Thanks for your reply.

Can you more explain how to create power table (with virtuoso simulation) like power table that generate with liberty NCX.



Based on PDK document the internal power is power disipated by Isc.