Power supply noise reduction scheme??

[jt_rf]

How to isolate on-chip sensitive circuits like BGR from switching circuits which switch at 100MHz but with package inductance create Very high frequency noise?


Can we use a onchip inductor to decouple the switching (noisy) circuit and the supply sensitive circuit?

any idea/document/links etc would be very useful.

advance thanks.

JT.

 

[k_90]

1.Star the power as close too the pad as possible.
1.1 Use a large (20u)substrate between the noisy/quite area and star it back to the pad.
2.Create as much space between noisy/quite circuits.
3. put minimum sized guard rings round all blocks.

 

[leo_o2]

Something more: use separated bonding/PAD for noisy circuit and quiescent circuit. And insert some GND PAD between them.

 

[jt_rf]

Thanks Leo & K_90 for your inputs.

I simulated using a separate PAD for switching and silent circuits. It works However, when connected at the top level, still there is noise coupling.

Should I use a altogether separate power supply pin for BGR?


again thanks for your inputs.

regards,
JT

 

[k_90]

They main point of staring back to the pad etc is to minimise the noise as much as possible, you'll never be able to eliminate it unless you use Deep Nwell to isolate it but that depends on the process you are using.

 

[jt_rf]

Thanks for your inputs.


regards,
JT