Power Supply Induced Jitter (PSIJ)

Every logic gate has an intrinsic relation of prop delay
to supply voltage. Supply ripple happens at low (by
gate-delay scale) frequency and is generally triangular.
So across one PS cycle you will traverse a range of
"observed prop delays". That is one element.

The input threshold of a CMOS logic gate also has a
supply sensitivity, being designed roughly VDD/2. Every
signal has a slew rate, also defined by supply -> IDss.
This slew rate is also a "transform" between voltage and
time. As you pass through the gate's linear region the
input slew rate (half of it, the time to cross threshold from
rest) and voltage noise amplitude produces a "time noise"
as it "reflects off the slope, like a canted mirror".

You can observe these in simulation easily of you stack
and PWL or AC sources and go tickle an inverter in
SPICE. With realistic modeling you can get a realistic
eye diagram.