power report issue with Power Compiler ...

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Arik

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Hi All

I am trying to do power analysis of a hierarchical design using Power Compiler. The problem is that I get different internal power values for one of the bottom-level subdesigns when I issue the Power Compiler report_power command from different levels of hierarchy. BTW I observed the same thing with net switching power values. So could anyone please explain me what's the reason ???

thx.
 

Right. I was faced with the similar problem with Astro Rail too. Hierarchical power analysis simply gave a wrong results. I had to flat the design to get the right numbers. BTW have you used top level .sdc to define the clock activities and have you propagated them through the whole hierarchy ?
 

thx moorhuhn for response !!!

I have used the top-level .sdc to define the clock activities but I'm not sure if I have propogated it through the whole hierarchy. Tell me please what means to propogate .sdc through design hierarchy and how it should be done ?
 

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