Power plane seperation

[ctzof]

Hello,
I am designing a high speed DAQ transceiver and I am in the stage of designing the stack. In the following picture you can see what Ive done already. High speed differential lines will be routed on S1, S2, S5, S3 and bottom layer TOP layer is going to be used for other lines and sps. I need a recommendation about the thickness of dielectrics of the ground and power planes. For me is it better to make them small as with this way I can reduce the total thickness of the board but what do you recommend. Which are the differences of using large and small thickness for the dielectrics in the power planes. Thanks

 

[KlausST]

Hi,

With high speed signals you may need specific trace impedance. Often in the range of 50...120 ohms. To achieve this it is easier with thin isolation layers.
I recommend to discuss your needs with your pcb manufacturer. They usually have the technical data of the used material, standard thickness of material, design guides and calculators.Be aware that the pcb manufacturers have production tolerances that may affect impedance.
To be able to check impedance after production you may route some spare signal lines in several layers with available connection at top or bottom where you can measure the true trace impedance. If possible route it at least 100mm in length.
For very sensible signals you may consider to route it directely between two gnd planes.

Klaus

 

[FvM]

PCB impedance calculators have been often mentioned at edaboard, e.g. in this thread https://www.edaboard.com/threads/290500/

PCB substrates and prepregs thickness must be chosen from available products, there aren't so much options for a 16 layer stackup.

PCBs are build sequentially around "cores". During this sequence, partial interconnects (buried vias) can be made. So the intended burried vias decide how to build the PCB. Preferably you'll discuss useful options with your PCB manufacturer.

At first sight, I don't understand why your "high speed" stackup has layer pairs (S1-S2) (S3-S4) without separating ground planes although there are pretty much planes in your design.

 

[ctzof]

Thanks for the answers. Regarding the question about the S1-S2 layers, this type of structure is proposed by others too for example here https://www.pcbway.com/blog/Engineering_Technical/PCB_Stackup_Planning___Simple.html you can find a similar structure for a 16 layer board. My question had to do only about the thickness of the dielectrics in power planes (PWR-GND). I read somewhere that making this dielectrics thin you can increase planar capacitance which is useful for decoupling. On the other hand many say that if you decrease this dielectric thickness you might encounter problems with thermal dissipation of the board. So whats the case?

 

[FvM]

Thanks for the answers. Regarding the question about the S1-S2 layers, this type of structure is proposed by others too for example here https://www.pcbway.com/blog/Engineeri...___Simple.html you can find a similar structure for a 16 layer board. My question had to do only about the thickness of the dielectrics in power planes (PWR-GND). I read somewhere that making this dielectrics thin you can increase planar capacitance which is useful for decoupling. On the other hand many say that if you decrease this dielectric thickness you might encounter problems with thermal dissipation of the board. So whats the case?

The 16 layer stackup in the link has 8 inner signal layers instead of 4 in your example, it is using planes as shielding means in a useful way.

Regarding layer thickness, yes you can use thinner substrates. Heat dissipation is mainly performed by copper rather than expoxy, so it doesn't cause problems. You should also think about acceptable PCB warping and required stability.

Thinnest standard substrate is 100 µm, downto to 50 µ is possible. As previously suggested, ask your manufacturer about available options.