banjo
Advanced Member level 2
I need to port a PowerPC 405GPr design from a daugther card to an embedded system on the main board. The External Bus Controller will drive three FPGAs. These FPGAs will be scattered across a fairly large board. Looking at the reference design from AMCC, they do not seem to buffer the address or data lines at all. They just seem to daisy chain all the chips together which seems like a controlled impedance nightmare.
Does anyone have experience buffering these lines? Is it required or not worth the effort? The clock for this external bus is only 33MHZ and the FPGAs will never be bus master, but always be the slaves.
Thanks.
Does anyone have experience buffering these lines? Is it required or not worth the effort? The clock for this external bus is only 33MHZ and the FPGAs will never be bus master, but always be the slaves.
Thanks.