power on reset (POR) design on chip

[konkon]

i design a POR with bandgap+resistor divider+comparator+delay .as the output of the bandgap is nearly 0 when the VDD is low,so there will be a pulse of reset which is not need.
can anyone help me? or send me some ieee papers on the power on reset to me?
my e-mail:tomsoya922@yahoo.com.cn
thanks in advance!

 

[megzhuy]

Does your circuit work like this? When the VDD begin to get higher and higher, bandgap work normally, after that, por start to work, then the chip begin to work.
If your chip work like this, you can use your own idea.

 

[Btrend]

u need a extra "rough" por (as compared to ur "bandgap por" which is accurate por) ckt which will function whenever bandgap is not working. and the final POR signal is the combination of (rough por)*(accurate por)