[SOLVED] power on reset for flip flop based counter

Hello,

I'm just starting out, so tell me if I am not saying this right. As I understand it (based on other posts), you can't depend upon the initial value of a flip flop. I have a set of jk flipflops with set/reset pins (CD4027B) and I wanted to know if the power-on-reset logic that I made makes sense.
1) is it true that you can't depend upon the initial value of a flip flop, or is this chip or technology (cmos vs ttl) dependent?
2) here is a falstad link to my por design (sort of, it is a bit simplified because the jk in falstad doesn't have set/reset pins and my actual project uses multiple jks chained together and fed from a 555). The wire hanging after the capacitor is meant to feed the reset pin.

The thing that has me sketched out is the connection from the transistor emitter back to it's base. It seems to work in falstad, but I'm wondering if anyone knows if this is insane and if there is an easier way to do this... Thanks!

An easy way to pull a wire high or low when power is applied (shown as the blue vertical line on the scope trace).



The 100k resistor is needed to discharge the capacitor when power is disconnected.

Values are not critical.

An alternative to the 100K is a diode across the charging resistor so when the supply drops it provides a path for the capacitor to quickly discharge. The diode makes it more responsive to short power breaks than a resistor could.

Brian.

Power-on reset schemes often presume some "hook" to
hang it on. For example, C-R presumes some things, like
that the supply has spent enough "low time" that the
network bleeds to its settled "0" state. Perhaps true in
the "normal" user case, powering up for the first time.
Not necessarily true in an ATE environment where you
are trying to blow through a pattern and then again at
another supply voltage; did you design in a one-second
"off dwell" requirement and your production test program
needs to be under 100mS, all done, per touchdown?

Similarly some AC-coupled schemes only work out to
some maximum risetime / minimum slew rate.

When I'm feeling extra paranoid I will combine an AC
and a DC-level POR scheme. Sometimes I use DC only
if I'm expecting a slow ramp (like, say, a POL converter
that I expect will be fed by an upstream soft-started
brick).

@brad and betwixt: Okay, that makes a lot more sense, thanks! I'm happy I don't need to shove an extra transistor on the board. So just to clarify, the current will roll through the capacitor, setting the output high. When the capacitor charges up, the current will have to go through the 100k resistor. Since the 100k and the 100 make a voltage divider with most of the voltage drop at the 100k, the output will be low. So I'll get a high pulse when the power comes on as the capacitor is charging. And when the power is off, the capacitor will discharge through the 100 resistor to ground. Thanks, that was exactly what I was looking for!