This is an interesting question, and I would like to know the answer myself, so I asked a very experienced Power Applications engineer. The first response (this post) is the simplest and most direct approach. This is a DC approach. Later we can think about the pulsed approach.
This will all be in terms of an nmos because it is easier to think about the polarities that way. You can adapt this approach for the pmos.This approach is based on using the functions of a power supply. Suppose you want to test your power nmos at 10A. Assume a somewhat larger than expected RDS(on), say 2 Ohm. Then 10A into 2 Ohm is 20V. Set your power supply to 20V. Next, with the supply set to 20V, and the current limit set to zero, short out the supply. The output voltage will go to zero. Next, slowly increase the currrent limit until you reach 10A. This is not bad for the supply. It can work all day like this, it is in current limit mode, and is now working as current source for you.
If you want a more accurate reading of the current limit, you can place a current meter inbetween the + and - leads from the supply.
After making the current meter measurement, remove the current meter. The current source from the supply won't change as long as you don't touch the dial for current limit.
Connect a low impedance to the gate of your power nmos, say 50 Ohm. This to provide ESD protection to the gate. Connect VGS to the power nmos, but start with VGS=0. Now slowly increase VGS until you get to VGS=10V. The drain of the nmos is connected to the + output of your supply.
As VGS is turned ON, the power nmos comes to life and sucks the 10A limit from the supply. You can read the voltage on the supply or use a DMM to read the voltage on the drain. Obviously, this voltage divided by 10A is your RDS(ON).
The only problem with this approach is the availability of a high current power supply. But really, the power FET is in its triode region and the Ids -Vds curve is linear, so you can do the test at different (lower) currents. Maybe make 3 measurements (at I = 0.5, 1.0, and 1.5A) to verify linearity. Vds/Ids should be pretty much constant.
I'll wait for feedback to make sure my idea isn't crazy, and then I'll ask someone else about making the pulsed measurement. Sometimes this is the only way to go because of the high powers involved. There are some guys that I work with that make these measurements all the time, and I am happy for the opportunity to learn more about it. It would also be good to hear from anyone who characterizes power FETS.