hktk
Junior Member level 3
I'm designing a PMU (Power Management Unit, including Buck and LDO) and there are several issues in the design:
1. voltage reference design for each block. Reference should be provide for each voltage conversion block, Buck or Ldo. But if only one bandgap reference is designed and connected to subblocks, the reference voltage will be interfere by the switching noise and spikes;
2. Circuit Topology for noise suppression. Noise/interference/EMI issues will be serious when all these block are integrated in single chip. One should par attention to grounding, shielding, de-coupling, in layout design, mentioned in the topic below:
.
But I think the subblocks (EA, Comparator, etc) should have both positive and negative PSR, introducing different circuit topology from conventional designs.
Can u give me some advises? Thanks!
1. voltage reference design for each block. Reference should be provide for each voltage conversion block, Buck or Ldo. But if only one bandgap reference is designed and connected to subblocks, the reference voltage will be interfere by the switching noise and spikes;
2. Circuit Topology for noise suppression. Noise/interference/EMI issues will be serious when all these block are integrated in single chip. One should par attention to grounding, shielding, de-coupling, in layout design, mentioned in the topic below:
.
But I think the subblocks (EA, Comparator, etc) should have both positive and negative PSR, introducing different circuit topology from conventional designs.
Can u give me some advises? Thanks!