Hi,
"loss" is ignorable when considering dielectric between power planes.
1) For sure thinner dielectric increases capacitance. But for most applications I recommend to just use the standard thickness.
2) The smaller one closer to the IC pin.
3) ... the goal is to get a "stable power supply", this means the supply should be low impednace even for very short current spikes.
You get this by considering the whole decoupling (capacitor) path as a loop.
It is NOT only important to get a short connection between FPGA_VCC and decoupling capacitor ...
but also:
* Capacitor, short trace to via(s)
* via(s) to a really solid GND plane
* GND_plane to FPGA_GND
* ... GND_plane to the signals leaving the FPGA
MIND:
In opposite to DC resistance ... you can NOT compensate a lenghty trace with a wider or thicker trace to get low impedance.
--> keep the whole loop (traces) as short as possible.
Trace with and trace thickness has rather low impact on the resulting loop impedance.
Klaus