Power Gating - Cadence RTL Compiler (RC)

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Bakazume

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I am starting now with Cadence RTL Compiler,

is it possible to implement Power Gating techniques using this tool ?
If yes, do I need a specific cell library ?

Thank you
 

yes you could with the CPF flow.
for power gating you need:
-a power switch which is a macro-analog component.
-isolation cell, AND gate could be enough (required).
-flop with retention value (not mandatory, depends of your design/functionality)

With the CPF, you will define which part of your design could be power on/off, and the tool will add isolation cell from/to this part, and you could request to change all flop into flop-with-retention, if your require to preserve the value during the power-off.
 
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