[SOLVED] Power FET avalanche energy

Hi, I have a question about power MOSFET avalanche energy and overvoltage.

Lets say, I have this FET:

https://www.infineon.com/dgdl/IPB04...b02d7&fileId=db3a304320d39d590121a517a48e0bb9

which has a maximum Vds voltage rating of 75V. Now, I run it at 60V but subject it to periodic overvoltage spikes, of say 20ns width up to 80 or 90V. The spikes will occur at a rate of about 30kHz. Will this damage the FET, or is there too little energy in these spikes to cause damage?

I've tried to limit the spikes with a snubber with some success.

Thanks.

The Applicati on Note AN 2012-03 "Datasheet Explanation" says referring to the avalanche characteristic curve (Figure 13 in the present datasheet):

Operating MOSFET under the conditions below the curve is allowed with consideration of the maximum junction temperature.

Click to expand...

In so far the operation is permitted, and there are in fact many designs, particularly in the low voltage range, that periodically pass the avalanche region. On the other hand, power semiconductors undergo aging and have limited lifetime. It's no so easy to determine, if periodical avalanche contributes to it.

FvM said:

The Applicati on Note AN 2012-03 "Datasheet Explanation" says referring to the avalanche characteristic curve (Figure 13 in the present datasheet):


In so far the operation is permitted, and there are in fact many designs, particularly in the low voltage range, that periodically pass the avalanche region. On the other hand, power semiconductors undergo aging and have limited lifetime. It's no so easy to determine, if periodical avalanche contributes to it.

Click to expand...

Is that graph for single pulse only however?

If I have a repeating pulse, it must change things. A 20ns, 90V pulse every 33us, I suppose is infrequent enough to not have a cumulative effect?

Figure 13 is also describing continuous operation, if the junction temperature is put in correctly.

Thanks FvM. How I see it...each pulse is survivable if within the ratings of Figure 13, and each pulse results in the heating of the FET. The limitation of a series of pulses is basically how much of a heating effect they have collectively. So, a simple calculation of the pulse energy being converted to heat, and how quickly the FET can be cooled. As long as each pulse stays within the limitations of Figure 13, its just a matter of mainting within the operating temperature of the FET. Am I correct?

If so, all this fear-mongering about over-voltage spikes instantly killing FETs is a little exaggerated? In reality the spikes would have to be pretty long (>3us) to cause damage.

For others looking for more information on this topic, I found a great document which describes how to calculate the temperature rise in the FET due to pulse overvoltage avalanche events (single pulse and series of pulses):

https://www.fairchildsemi.com/an/AN/AN-9034.pdf

The message of the Fairchildsemi AN is simple, I think: There's junction temperature and nothing else. That sounds plausible at first sight and seems to be validated by the empirical observable behaviour of modern MOSFETs.

But there are prerequisites: The breakdown must occur uniformly distributed over the MOSFET structure. The positive temperature coefficient will basically promote uniform distribution, but a MOSFET with "light" structural faults might defy the assumptions. Hopefully it would have been sorted out during the extensive individual tests of MOSFET components.

I have still a small doubt that continuous avalanche operation might reduce MTBF as a statistical quantity. Of course, if the avalanche energy is very small compared to rated values, the effect should be negletible.